Z87200 Datasheet, PDF(26/54 Page) Zilog, Inc. – Spread-Spectrum Transceiver

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Z87200 Datasheet, PDF (26/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

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Z87200

Spread-Spectrum Transceiver

Zilog

OUTPUT SIGNALS (Continued)

pairs. Note that, when the Z87200 is operated in burst

mode, the first bit of RXQOUT in each burst will be invalid.

/RXDRDY (Pin 54)

Receiver Data Ready Bar. /RXDRDY is provided as a re-

ceiver timing signal. /RXDRDY is normally set high and

pulses low during the baseband sampling clock cycle

when a new RXOUT signal is generated.

RXSPLPLS (Pin 53)

Receiver Sample Pulse. RXSPLPLS is an output timing

signal that provides internal timing information to the user.

RXSPLPLS is the internally generated baseband sampling

clock, referenced either externally or internally according

to the setting of bit 0 of address 01H. All receiver functions,

excluding those in the Downconverter, trigger internally on

the rising edge of RXSPLPLS.

RXSYMPLS (Pin 52)

Receiver Symbol Pulse. RXSYMPLS is an output signal

that provides the user internal timing information relative to

the detection/correlation of symbols. Symbol information

from the PN Matched Filter, DPSK Demodulator, and Out-

put Processor is transferred on the rising edge of RXS-

PLPLS preceding the falling edge of RXSYMPLS.

RXACTIVE (Pin 83)

Receiver Active. A high level on RXACTIVE indicates that

the receiver has detected an Acquisition/Preamble symbol

and is currently receiving data symbols. RXACTIVE will be

set high one bit period before the first rising edge of

/RXDRDY, indicating that the first data bit is about to ap-

pear at the RXOUT, RXIOUT, and RXQOUT pins. RXAC-

TIVE will be set low immediately following the last rising

edge of /RXDRDY, indicating that the last data bit of the

burst has been output at the RXOUT, RXIOUT, and RX-

QOUT pins. RXTEST7-0 (Pins 41-48)

These pins provide access to 16 test points within the re-

ceiver as shown in The pin outputs are selected according

to the value in bits 3-0 of address 38H and the assignments

shown in When one of these 4-bit values is written into ad-

dress 38H, the corresponding function becomes available

at the RXTEST7-0 outputs. The RXTEST7-0 bus is a tri-

state bus and is controlled by the OEN input. Note that the

validity of the RXTEST7-0 outputs at RXIFCLK speeds

greater than 20 MHz is dependent on the output selected:

outputs that change more rapidly than once per symbol

may be indeterminate.

Table 4. Receiver Test Functions

Bits 3-0 of 38H

RXTEST7-0 Output

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

MFQIN 2-0 Matched Filter Q Input MFIN2-0 Matched Filter I Input

Pk-Power9-2 MF Peak Magnitude Output (Changes Once Per Symbol)

COS7-0 Cosine Output of NCO (Changes Every Cycle of RXIFCLK)

SIN7-0 Sine Output of NCO (Changes Every Cycle of RXIFCLK)

DCIOUT16-9 Downconverter I Channel Output (Changes at RXIFCLK Rate)

DCQOUT16-9 Downcounter Q Output (Changes at RXIFCLK Rate)

ISUM 9-2 Matched Filter I Output (Changes Twice Per Chip)

QSUM9-2 Matched Filter Q Output (Changes Twice Per Chip)

POWER9-2 MF Magnitude Output (Changes Twice Per Chip)

ISUM7-0 MF Viewpoint I Output (Changes Twice Per Chip)

QSUM7-0 MF Viewpoint Q Output (Changes Twice Per Chip)

Pk-ISUM7-0 MF Peak I Channel Output (Changes Once Per Symbol)

Pk-QSUM7-0 MF Peak Q Channel Output (Changes Once Per Symbol)

DOT16-9 Dot Product (Changes Once Per Symbol)

CROSS16-9 Cross Product (Changes Once Per Symbol)

TXFBK7-0 Loopback Test Output

4-26

DS96WRL0400

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