Z87200 Datasheet, PDF (17/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Z87200
Spread-Spectrum Transceiver
The Z87200 contains a fully programmable 64-tap com-
plex (dual I and Q channel) PN Matched Filter with coeffi-
cients which can be set to ±1 or zero according to the con-
tents of either the Acquisition/Preamble or Data Symbol
Code Coefficient Registers. By setting the coefficients of
the end taps of the filter to zero, the effective length of the
filter can be reduced for use with PN codes shorter than 64
bits. Power consumption may also be reduced by turning
off those blocks of 7 taps for which all the coefficients are
zero, using bits 6-0 of address 39H. Each ternary coeffi-
cient is stored as a 2-bit number so that a PN code of
length N is stored as N 2-bit non-zero PN coefficients. Note
that, as a convention, throughout this document the first
PN Matched Filter tap encountered by the signal as it en-
ters the I and Q channel tapped delay lines is referred to
as “Tap 0.” Tap 63 is then the last tap of the PN Matched
Filter.
The start of each burst is expected to be a single symbol
PN-spread by the Acquisition/Preamble code. The receiv-
er section of the Z87200 is automatically configured into
acquisition mode so that the Matched Filter Acquisi-
tion/Preamble Coefficients stored in addresses 07_H to 16_H
are used to despread the received signal. Provided that
this symbol is successfully detected, the receiver will auto-
matically switch from acquisition mode, and the Matched
Filter Data Symbol Coefficients stored in addresses 17_H to
26_H will then be used to despread subsequent symbols.
To allow the system to sample the incoming signal asyn-
chronously (at the I.F. sampling rate) with respect to the
PN spreading rate, the PN Matched Filter is designed to
operate with two signal samples (at the baseband sam-
pling rate) per chip. A front end processor (FEP) operating
on both the I and Q channels averages the incoming data
over each chip period by adding each incoming baseband
sample to the previous one:
FEP_OUT = FEP_IN (1 + z ^–1)
Zilog
After the addition, the output of the FEP is rounded to a 3-
bit offset 2’s complement word with an effective range of
±3.5 such that the rounding process does not introduce
any bias to the data. The FEP can be disabled by setting
bit 0 of address 27_H to 1, but for normal operation the FEP
should be enabled.
The PN Matched Filter computes the cross-correlation be-
tween the I and Q channel signals and the locally stored
PN code coefficients at the baseband sampling rate, which
is twice per chip. The 3-bit signals from each tap in the PN
Matched Filter are multiplied by the corresponding coeffi-
cient in two parallel tapped delay lines. Each delay line
consists of 64 multipliers which multiply the delayed
3-bit signals by zero or ±1 according to the value of the tap
coefficient. The products from the I and Q tapped delay
lines are added together in the I and Q Adders to form the
sums of the products, representing the complex cross-cor-
relation factor. The correlation I and Q outputs are thus:
n = 63
Σ Output_{(I, Q)}= Data_{n(I, Q)} * Coefficient_{n(I, Q)}
n=0
These I and Q channel PN Matched Filter outputs are 10-
bit signals, with I and Q channel programmable viewports
provided to select the appropriate output bits as the 8-bit
inputs to the Power Detector and DPSK Demodulator
blocks. Both I and Q channel viewports are jointly con-
trolled by the data stored in bits 1-0 of address 28_H and are
saturation protected.
Two power saving methods are used in the PN Matched
Filter of the Z87200. As discussed previously, the first
method allows power to be shut off in the unused taps of
the PN Matched Filter when the filter length is configured
to be less than 64 taps. The second method is a propri-
etary technique that (transparently to the user) shuts down
the entire PN Matched Filter during portions of each sym-
bol period.
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DS96WRL0400