Z87200 Datasheet, PDF (30/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Z87200
Spread-Spectrum Transceiver
Zilog
CONTROL REGISTERS (Continued)
ficients, each requiring 2 bits of storage according to the
mapping shown in Table 8.
Table 8. PN Matched Filter Tap Values
Tap Bits 1,0
X
0
0
1
1
1
Tap Coeff
0
+1
-1
As a convention, Tap 0 is the first tap as the received sig-
nal enters the PN Matched Filter, and Tap 63 is the last. All
active taps of the PN Matched Filter, from Tap 0 up to Tap
(N-1), where N is the length of the PN code, should be pro-
grammed with tap coefficient values of +1 or -1 according
to the PN code sequence. Setting the end coefficients of
the PN Matched Filter registers to zero values permits the
effective length of the filter to be made shorter than 64
taps.
Addresses 07_H through 16_H:
Matched Filter Acquisition/Preamble Symbol
Coefficients
Addresses 07_H to 16_H contain the 64 2-bit Acquisition/Pre-
amble PN code coefficient values. The 128 bits of informa-
tion are stored in 16 8-bit registers at addresses 07_H to 16_H
as shown in Table 8.
Table 9. Acquisition/Preamble Coefficient Storage
Bits 7,6
Coeff. 63
Bits 7,6
Coeff. 59
---
---
Bits 7,6
Coeff. 7
Bits 7,6
Coeff. 3
Address 16_H
Bits 5,4
Bits 3,2
Coeff. 62 Coeff. 61
Address 15_H
Bits 5,4
Bits 3,2
Coeff. 58 Coeff. 57
---
---
---
---
Address 08_H
Bits 5,4
Bits 3,2
Coeff. 6
Coeff. 5
Address 07_H
Bits 5,4
Bits 3,2
Coeff. 2
Coeff. 1
Bits 1,0
Coeff. 60
Bits 1,0
Coeff. 56
---
---
Bits 1,0
Coeff. 4
Bits 1,0
Coeff. 0
Addresses 17_H through 26_H:
Matched Filter Data Symbol Coefficients
Addresses 17_H to 26_H contain the 64 2-bit Data Symbol
PN code coefficient values. The 128 bits of information are
stored in 16 8-bit registers at addresses 17_H to 26_H as
shown in The contents of addresses 17_H to 26_H are inde-
pendent of and not affected by the contents of addresses
07_H to 16_H.
Table 10. Data Symbol Coefficient Storage
Bits 7,6
Coeff. 63
Bits 7,6
Coeff. 59
---
---
Bits 7,6
Coeff. 7
Bits 7,6
Coeff. 3
Address 26_H
Bits 5,4 Bits 3,2
Coeff. 62 Coeff. 61
Address 25_H
Bits 5,4 Bits 3,2
Coeff. 58 Coeff. 57
---
---
---
---
Address 18_H
Bits 5,4 Bits 3,2
Coeff. 6 Coeff. 5
Address 17_H
Bits 5,4 Bits 3,2
Coeff. 2 Coeff. 1
Bits 1,0
Coeff. 60
Bits 1,0
Coeff. 56
---
---
Bits 1,0
Coeff. 4
Bits 1,0
Coeff. 0
Address 27_H:
Bit 0 — Front End Processor Disable
The Front End Processor (FEP) averages the two base-
band samples per chip by adding consecutive pairs of
samples. The function may be disabled for test purposes
by using this bit: when set low, the FEP is enabled and in
its normal mode of operation; when set high, the FEP is
disabled.
Power Estimator Registers
Address 28_H:
Bits 1-0 — Matched Filter Viewport Control
The Z87200 incorporates viewport (data selector) circuitry
to select any eight consecutive bits from the 10-bit outputs
of the PN Matched Filter as the 8-bit inputs to the Power
Estimator and DPSK Demodulator blocks. The Symbol
Tracking Processor, however, operates on the full 10-bit
PN Matched Filter outputs before the viewport is applied.
The signal levels of the PN Matched Filter output reflect
the number of chips per symbol and the signal-to-noise ra-
tio of the signal. Setting the viewport thus effectively nor-
malizes the PN Matched Filter outputs prior to further pro-
cessing. The unsigned value, n, of bits 1-0 of address 28_H
determines the 8-bit input to the Power Estimator and
DPSK Demodulator blocks as the 10-bit PN Matched Filter
output divided by 2ⁿ. Equivalently, bits 1-0 control the
viewport of the PN Matched Filter output as shown in Note
4-30
DS96WRL0400