Z87200 Datasheet, PDF (28/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Z87200
Spread-Spectrum Transceiver
CONTROL REGISTERS
Setting the Control Registers
The majority of the Z87200 control registers are complete-
ly independent and can be set or modified in any order.
Two exceptions, however, exist:
s First, any time that the NCO is disabled, either through
use of pin MNCOEN or bit 0 of address 37_H, the
frequency control word must be reloaded, either through
use of pin MFLD or bit 0 of address 00_H, once the NCO
is re-enabled.
s Second, setting bit 2 of address 37_H to zero to disable
the receiver will also cause the data in address 38_H to be
set to zero, thereby possibly changing the receiver test
point(s) that will be observed on the RXTEST pins.
Address 38_H must be loaded with its desired value after
bit 2 of address 37_H is again set to 1.
Downconverter Registers
Address 00_H:
Bit 0 — Frequency Control Word Load
This bit is used to load a frequency control value into the
NCO, thereby changing its output frequency. The signal is
internally synchronized to RXIFCLK to avoid intrinsic race
or hazard timing conditions.
The loading of the NCO may be performed by various
means. Setting this bit provides a synchronized internal
means to control update of the NCO. Alternatively, the
MFLD pin or the Z87200’s programmable loop filter timing
circuitry may be used.
The MFLD input and bit 0 of address 00_H are logically
ORed together so that, when either one is held low, a rising
edge on the other triggers the frequency load function
manually. The rising edge of this bit is synchronized inter-
nally so that, on the following sixth rising edge of RXIF-
CLK, the frequency control word is completely registered
into the NCO accumulator. The frequency load command
must not be repeated until after a delay of six RXIFCLK cy-
cles.
Address 01_H:
Bit 0 — Manual Sample Clock Enable
This bit selects the source of the internal baseband sam-
pling clock, which should be at twice the nominal PN chip
rate. The clock reference may be either supplied externally
by RXMSMPL or generated internally from RXIFCLK.
Zilog
When this bit is set high, the baseband sampling rate of the
receiver is controlled by the external RXMSMPL signal.
When it is set low, the sampling clock is generated inter-
nally (at a rate determined by the Sample Rate Control
counter and set by bits 5-0 of address 02_H) and the
RXMSMPL input is ignored.
Bit 1 — Invert Loop Filter Value
This bit allows the sign of the output signal from the loop
filter to be inverted, thereby negating the value of the sig-
nal. The capability to invert the loop filter value permits the
carrier frequency error component generated in the de-
modulator to be either added to or subtracted from the Fre-
quency Control Word of the NCO. The correct setting will
depend on several factors, including whether high-side or
low-side downconversion is used.
When this bit is set low, the loop filter output is negated be-
fore being summed with the Frequency Control Word of
the NCO and is thus subtracted from the FCW; when this
bit is set high, the loop filter output is not negated and is
added to the FCW.
Bit 2 — NCO Accumulator Carry In
This bit is primarily used as an internal test function and
should be set low for normal operation. When this bit is set
high, 1 LSB is added to the NCO accumulator each clock
cycle. When it is set low, the NCO accumulator is not af-
fected.
Bit 3 — Two’s Complement Input
The RXIIN_7-0 and RXQIN_7-0 input signals can be in either
two’s complement or offset binary formats. Since all inter-
nal processing in the device operates with two’s comple-
ment format signals, it is necessary to convert the RXIIN_7-
0 ^{and RXQIN}7-0 ^{inputs in offset binary format to two’s com-}
plement format by inverting the MSBs.
When this bit is set high, the device expects two’s comple-
ment format inputs on RXIIN_7-0 and RXQIN_7-0. When it is
set low, the device expects offset binary format on RXIIN_7-
0 ^{and RXQIN}7-0^{. In two’s complement format, the 8-bit in-}
put values range from –128 to +127 (80_H to 7F_H); in offset
binary format, the values range from 0 to +255 (00_H to
FF_H).
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