Z87200 Datasheet, PDF (37/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Zilog
Z87200
Spread-Spectrum Transceiver
When input signal MTXEN is set low, bit 1 of address 37 Note that the reset sequence that occurs when the receiv-
H
controls the activity of the transmit circuitry and, when er is disabled will also reset the contents of address 38_H to
4 ^{MTXEN is set low, bit 1 controls this function. When either a value of 0. If the RXTEST7-0 bus is to be used to observe}
bit 1 or MTXEN (whichever is in control, as defined above) any function other than the PN Matched Filter I and Q in-
goes low, a reset sequence occurs on the following TXIF- puts, then the appropriate value must be rewritten.
CLK cycle to virtually disable all of the transmitter data
path, although the user programmable control registers
are not affected by the power down sequence.
Address 39_H:
Bits 6-0 — Matched Filter Power Saver
Bit 2 — Receiver Enable
The function of this bit is to allow power consumed by the
operation of the receiver circuitry to be minimized when the
device is not receiving. With the instantaneous acquisition
properties of the PN Matched Filter, it is often desirable to
shut down the receiver circuitry to reduce power consump-
tion, resuming reception periodically until an Acquisi-
tion/Preamble symbol is acquired. Setting bit 2 low reduc-
es the power consumption substantially. When bit 2 is set
high, the receiver will automatically power up in acquisition
The data stored in bits 6-0 of address 39_H allows the un-
used sections of the PN Matched Filter to be turned off
when the PN Matched Filter is configured to be less than
64 taps long for data symbols. All taps are always fully
powered when the device is in acquisition mode.
The PN Matched Filter is split into seven 9-tap sections,
and the power to each section is controlled by the settings
of bits 6-0 of address 39_H, as shown in Table 19.
Table 19. Matched Filter Tap Power Control
mode regardless of its prior state when it was powered
down. Bit 2 of address 37_H operates independently of bits
1 and 0 of address 37_H, where these signals have similar
control over the transmit and NCO circuitry, respectively.
Bit in Addr. 39_H
0
1
MF Taps Controlled
1-9
10-18
Bit 2 of address 37_H performs the same function as MRX-
EN, and these two signals are logically ORed together to
2
3
form the overall control function. When bit 2 of address 37_H
4
is set low, MRXEN controls the activity of the receiver cir-
5
cuitry and, when MRXEN is set low, bit 2 of address 37_H
6
controls the activity of the receiver circuitry. When either bit
19-27
28-36
37-45
46-54
55-64
2 or MRXEN (whichever is in control, as defined above)
goes low, a reset sequence begins on the following RXIF-
CLK cycle and continues through a total of six RXIFCLK
cycles to virtually disable all of the receiver data paths. The
user- programmable control registers are not affected by
the power down sequence, with the exception of
RXTEST_7-0 (address 38_H), which is reset to 0. If the
RXTEST_7-0 bus is being used to read any function other
than the PN Matched Filter I and Q inputs, the value must
be rewritten.
Power control is not provided for Tap 0, the first tap of the
PN Matched Filter, since Tap 0 is always used no matter
what the PN code length. Setting a bit high in bits 6-0 of ad-
dress 39_H turns off the power to the corresponding block
of taps of the PN Matched Filter. The power should only be
turned off to those blocks of taps for which all the tap coef-
ficients in that block have been set to zero
Address 3A_H:
Receiver Data Symbols per Burst (bits 15-8)
Address 38_H:
Bits 3-0 — RXTEST_7-0 Function Select
The data stored in bits 3-0 of address 38_H selects the sig-
nal available at the RXTEST_7-0 bus (pins 41-48). These
pins provide access to 16 test points within the receiver ac-
cording to the data stored in bits 3-0 of address 38_H and
the assignments shown in The validity of the RXTEST_7-0
outputs at RXIFCLK speeds greater than 20 MHz is de-
pendent on the output selected: outputs that change more
rapidly than once per symbol may be indeterminate.
The data stored as two bytes in addresses 2E_H (LS byte)
and 3A_H (MS byte) defines the number of data symbols per
burst. This unsigned value must range from 3 to 65,535
(0003_H to FFFF_H), and the number of data symbols per
burst will be this value minus 2, giving a range of 1 to
65,533. Note that the range is slightly different from that in
the transmitter. Once the number of received data symbols
processed exceeds this number, the burst is assumed to
have ended and the Z87200 immediately returns to acqui-
sition mode to await the next burst.
DS96WRL0400
4-37