Z87200 Datasheet, PDF (38/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Z87200
Spread-Spectrum Transceiver
Zilog
CONTROL REGISTERS (Continued)
Address 3B_H:
Bit 0 — Matched Filter Loopback Enable
The Z87200 incorporates a loopback capability that feeds
the encoded and spread transmit signals TXIOUT and TX-
QOUT directly into the PN Matched Filter inputs. This test
mode allows the baseband portion of the system to be test-
ed independently of the BPSK/QPSK Modulator and
Downconverter.
Setting bit 0 of address 3B_H high enables this loopback
path; setting it low puts the device into its normal operating
mode.
Bit 1 — I.F. Loopback Enable
The Z87200 incorporates a loopback capability that feeds
the encoded, spread and modulated transmit signal
TXIFOUT_7-0 directly into the receiver RXIIN_7-0 input. This
test mode allows the entire digital portion of the system to
be tested. Since only the I channel is provided as an input,
I.F. loopback requires that the PN chip rate and RXIFCLK
rate be consistent with Direct I.F. Sampling Mode.
Setting bit 1 of address 3B_H high enables this loopback
path; setting it low puts the device into its normal operating
mode.
Bits 3-2 — Receiver Overlay Select
The Z87200 incorporates programmable overlay code
generators in both the transmitter and receiver. When en-
abled, the selected receiver overlay code is subtracted
from the data symbols, one overlay bit per symbol in both
BPSK and QPSK modes. No synchronization beyond the
burst acquisition synchronization that is intrinsic to opera-
tion of the Z87200 is required since the overlay code gen-
erators in both the transmitter and the receiver are auto-
matically reset at the start of each burst. The addition of
the overlay code randomizes the transmitted data se-
quence to guarantee that the spectrum of the transmitted
signal will be adequately whitened and will not contain a
small number of spectral lines even when the data itself is
not random.
Three transmit and receive overlay codes can be selected,
where they are each maximal length sequences with
lengths of 63, 511 and 1023 symbols. The receiver overlay
codes are enabled and selected by the settings of bits 3-2
of address 3B_H, as shown in Table 19.
Table 20. Receiver Overlay Code Select
Bits 3-2 in
Addr. 3B_H
0
1
2
3
Overlay Code Length
and Polynomial
Overlay Code Disabled
63: 1 +x^-2+x^-3+x^-5+x^-6
511: 1 +x^-2+x^-3+x^-5+x^-9
1023: 1 + x^-2+x^-3+x^-5+x^-10
Addresses 3C_H through 3F_H: Unused
Transmit Control Registers
Address 40_H:
Bit 0 — Transmit BPSK
This bit configures the transmitter for either BPSK or
QPSK mode transmission. and differential encoding.
If programmed for BPSK mode, data is requested by the
Z87200 by a rising edge of output signal TXBITPLS, where
TKBITPLS is generated once per symbol, one chip period
before the end of the current symbol. At the end of the
symbol duration, the TXIN data is latched into the device.
TXBITPLS falls low immediately following the rising edge
of TXIFCLK, which latches the TXIN value, and is generat-
ed repeatedly at the symbol rate as long as the input signal
MTXEN remains high.
In QPSK mode, data is requested by the Z87200 by a ris-
ing edge of output signal TXBITPLS, where this signal is
generated in this mode twice per symbol, first one chip pe-
riod before the middle of the symbol and then one chip pe-
riod before the end of the symbol. TXBITPLS requests the
data exactly one chip cycle before latching the TXIN data
into the device. TXBITPLS falls low immediately following
the rising edge of TXIFCLK, which latches the TXIN value.
When bit 0 of address 40_H is set low, the transmitter is con-
figured in QPSK mode; when it is set high, the transmitter
is configured in BPSK mode.
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DS96WRL0400