Z87200 Datasheet, PDF (29/54 Pages) Zilog, Inc. – Spread-Spectrum Transceiver

Zilog
Z87200
Spread-Spectrum Transceiver
Bits 7-4 — Integrate and Dump Filter Viewport Control
The Z87200 incorporates viewport (data selector) circuitry
to select any three consecutive bits from the 14-bit output
of the Integrate and Dump (I & D) Filters in the Downcon-
verter block as the 3-bit inputs to the dual-channel PN
Matched Filter. The signal levels of the Integrate and
Dump Filter I and Q outputs reflect the input signal levels
and the number of samples integrated before the filter con-
tents are “dumped,” where the number of samples is deter-
mined by the baseband sampling rate (nominally, twice the
PN chip rate) and the I.F. sampling rate (RXIFCLK). Set-
ting the viewport thus effectively normalizes the I & D Filter
outputs before further processing. The unsigned value, n,
of bits 7-4 of address 01_H determines the 3-bit inputs to the
PN Matched Filter as the14-bit I & D Filter outputs divided
by 2ⁿ. Equivalently, bits 7-4 control the viewport of the In-
tegrate and Dump Filter outputs as shown in Note that
viewport control affects both I and Q channels of the Inte-
grate and Dump Filters.
Table 6. Integrate & Dump Filter Viewport Control
Bits 7-4
0_H
1_H
2_H
3_H
•••
•••
A_H
B_H
I & D Bits Output to Matched Filter
2-0
3-1
4-2
5-3
•••
•••
12-10
13-11
Saturation protection is implemented for those cases when
the Integrate and Dump Filter output signal level overflows
the scaled range selected for the PN Matched Filter. When
the scaled value range is exceeded, the saturation protec-
tion limits the output word to the maximum or minimum val-
ue of the range according to whether the positive or nega-
tive boundary was exceeded.
Address 02_H:
Bits 5-0 — Receiver Baseband Sampling (Dump) Rate
Control
The baseband sampling rate should be set to twice the
nominal PN chip rate of the received signal and must be
less than or equal to half the rate of RXIFCLK. When bit 0
of address 01_H is set low, the baseband sampling clock for
the Integrate and Dump Filter and all subsequent receiver
circuitry is referenced to RXIFCLK and generated internal-
ly. The receiver baseband sampling rate is then set to the
frequency of RXIFCLK/(n+1), where n is the value stored
in bits 5-0 and must range from 1 to 63. This feature is use-
ful in cases where a specific sample rate is required that is
an integer sub-multiple of f_RXIFCLK. In cases where a sam-
ple rate is required that is not an integer sub-multiple of
f_RXIFCLK, an external baseband sampling rate can be pro-
vided by the RXMSMPL input.
Addresses 03_H through 06_H:
4
NCO Frequency Control Word
The Z87200’s internal NCO is driven by a frequency con-
trol word that is the sum of the frequency discriminator er-
ror value (generated in the demodulator) and the 32-bit fre-
quency control word (FCW) stored in this location. The four
8-bit registers at addresses 03_H to 06_H are used to store
the 32-bit frequency control word as shown in The LSB of
each byte is stored in bit 0 of each register.
Table 7. Integrate & Dump Filter Viewport Control
ADDR06H ADDR 05H ADDR04H
Bits 31-24 Bits 23-16 Bits 15-8
ADDR03H
Bits 7-0
The NCO frequency is then set by the FCW according to
the following formula:
f_NCO =
_f^R_^X_^I_^FC__^LK__x_F_CW
2³²
In order to avoid in-band aliasing, f_NCO must not exceed
50% of f_RXIFCLK; normally, the FCW should be set so that
f_NCO does not exceed ~35% of f_RXIFCLK. While this limita-
tion may seem to restrict use of the NCO, higher I.F. trans-
mit or receive frequencies can generally be achieved by
using aliases resulting from digital sampling. The signal
bandwidth with respect to f_RXIFCLK, the modulation type,
and the use of Direct I.F. or Quadrature Sampling Mode
also restrict the choice of NCO frequency, Theory of Oper-
ation.
PN Matched Filter Registers
Despreading of the received signal is accomplished in the
Z87200 with a dual (I and Q channel) PN Matched Filter.
Furthermore, the Z87200 is designed for burst signal oper-
ation, where each data burst begins with an Acquisi-
tion/Preamble symbol and is then followed by the actual in-
formation data symbols. Two separate and independent
PN codes can be employed, one for the Acquisition/Pre-
amble symbol, the other for the information symbols. Ac-
cordingly, the PN Matched Filter is supported by two PN
code registers to independently allow the programming of
two distinct codes up to 64 chips in length. The PN codes
are represented as a sequence of ternary-valued tap coef-
DS96WRL0400
4-29