XPS16550 Datasheet, PDF (9/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
XPS 16550 UART Register Definition
XPS 16550 UART Interface
The internal registers of the XPS 16550 UART are offset from the base address C_BASEADDR.
Additionally, some of the internal registers are accessible only when bit 7 of the Line Control Register
(LCR) is set. The XPS 16550 UART internal register set is described in Table 4.
Table 4: XPS 16550 UART Registers
Register Name
LCR(7)+ C_BASEADDR
+ Address
Access
Receiver Buffer Register (RBR)
Transmitter Holding Register (THR)
Interrupt Enable Register (IER)
Interrupt Identification Register (IIR)
FIFO Control Register (FCR)⁽³⁾
FIFO Control Register^{(2), (3)}
Line Control Register (LCR)
Modem Control Register (MCR)
Line Status Register (LSR)
Modem Status Register (MSR)
Scratch Register (SCR)
Divisor Latch Register (DLL)
Divisor Latch Register (DLM)
0 + C_BASEADDR + 0x1000
0 + C_BASEADDR + 0x1000
0 + C_BASEADDR + 0x1004
0 + C_BASEADDR + 0x1008
X + C_BASEADDR + 0x1008
1 + C_BASEADDR + 0x1008
X⁽¹⁾ + C_BASEADDR + 0x100C
X⁽¹⁾ + C_BASEADDR + 0x1010
X⁽¹⁾ + C_BASEADDR + 0x1014
X⁽¹⁾ + C_BASEADDR + 0x1018
X⁽¹⁾ + C_BASEADDR + 0x101C
1 + C_BASEADDR + 0x1000
1 + C_BASEADDR + 0x1004
Read
Write
Read/Write
Read
Write
Read
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Notes:
1. X denotes a don’t care
2. FIFO Control Register is write only in the National PC16550D
3. 16450 UART mode implementation does not include this register
XPS 16550 UART Register Logic
This section tabulates the internal XPS 16550 UART registers, including their reset values (if any).
Please refer to the National Semiconductor PC16550D UART with FIFOs data sheet (June, 1995) for a
more detailed description of the register behavior.
Receiver Buffer Register
This is an 8-bit read register as shown in Figure 3. The Receiver Buffer Register contains the last
received character. The bit definitions for the register are shown in Table 5. The offset and accessibility
of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 3
Reserved
RBR
0
23 24 25 26 27 28 29 30 31
Figure 3: Receiver Buffer Register (RBR)
DS577 April 18, 2007
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