XPS16550 Datasheet, PDF (6/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Table 1: XPS 16550 UART I/O Signals (Contd)
Port
Signal Name
Interface I/O
P46 rclk
P47 sin
P48 sout
P49 xin
P50 xout
P51 ctsN
P52 dcdN
P53 dsrN
P54 dtrN
P55 riN
P56 rtsN
P57 ddis
P58 out1N
P59 our2N
P60 rxrdyN
P61 txrdyN
Serial
I
Serial
I
Serial
O
Serial
I
Serial
O
Modem
I
Modem
I
Modem
I
Modem
O
Modem
I
Modem
O
User
O
User
O
User
O
User
O
User
O
Initial
State
-
-
1
-
~xin
-
-
-
1
1
1
1
1
1
0
Description
Receiver 16x clock (Optional,
may be driven by baudoutN
under control of the
C_HAS_EXTERNAL_RCLK
parameter)
Serial data input
Serial data output
Baud rate generator reference
clock (Optional, may be driven
by SPLB_Clk under control of
the C_HAS_EXTERNAL_XIN
parameter)
Inverted xin
Clear to send (active low)
Data carrier detect (active low)
Data set ready (active low)
Data terminal ready (active low)
Ring indicator (active low)
Request to send (active low)
Driver disable. Low when CPU is
reading XPS UART
User controlled output
User controlled output
DMA control signal
DMA control signal
XPS 16550 UART Design Parameters
To allow the user to create a XPS 16550 UART that is uniquely tailored for the user’s system, certain
features are parameterizable in the XPS 16550 UART design. This allows the user to have a design that
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DS577 April 18, 2007
Product Specification