XPS16550 Datasheet, PDF (8/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Parameter - Port Dependencies
The dependencies between the XPS 16550 UART core design parameters and I/O signals are described
in Table 3. In addition, when certain features are parameterized out of the design, the related logic will
no longer be a part of the design. The unused input signals and related output signals are set to a
specified value.
Table 3: Parameter-Port Dependencies
Generic
or Port
Name
Affects Depends Relationship Description
Design Parameters
G4
C_SPLB_DWIDTH
P9, P12,
P35
-
Affects the size of the PLB data bus
G5
C_SPLB_AWIDTH
P5
-
Affects the size of the PLB address
bus
G7
C_SPLB_MID_WIDTH
P7
G8
Affects the width of the PLB master
ID
G8
C_SPLB_NUM_MASTERS
P38,
P39,
P40
-
Identify the specific master on the
PLB
G11 C_HAS_EXTERNAL_XIN
P49
-
Connects xin to baudoutN
G12 C_HAS_EXTERNAL_RCLK
P46
-
Connects rclk to SPLB_Clk
I/O Signals
P5
PLB_ABus[0:C_SPLB_AWIDTH -
1]
-
G5
Width varies with the size of the PLB
address bus
P7
PLB_masterID[0:
C_SPLB_MID_WIDTH - 1]
-
G7
Width varies with the size of the
number of masters on the PLB
P9
PLB_BE[0:[C_SPLB_DWIDTH/8] -
1]
-
G4
Width varies with the size of the PLB
data bus
P12
PLB_wrDBus[0:C_SPLB_DWIDTH
- 1]
-
G4
Width varies with the size of the PLB
data bus
P35 Sl_rdBus[0:C_SPLB_DWIDTH - 1]
-
G4
Width varies with the size of the PLB
data bus
P38
Sl_MBusy[0:C_SPLB_NUM_MAST
ERS - 1]
-
G8
Width varies with the number of
masters on the PLB
P39
Sl_MWrErr[0:C_SPLB_NUM_MAS
TERS - 1]
-
G8
Width varies with the number of
masters on the PLB
P40
Sl_MRdErr[0:C_SPLB_NUM_MAS
TERS - 1]
-
G8
Width varies with the number of
masters on the PLB
P46 rclk
This input is unconnected and rclk is
P3
G12 connected to baudoutN, if
C_HAS_EXTERNAL_RCLK = 0
P49 xin
This input is unconnected and xin is
P45
G11 connected to SPLB_Clk, if
C_HAS_EXTERNAL_XIN = 0
8
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DS577 April 18, 2007
Product Specification