XPS16550 Datasheet, PDF (14/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Table 11: Modem Control Register Bit Definitions (Contd)
Bit
Name
Access
Reset Value
Description
28
Out2
Read/Write
29
Out1
Read/Write
30
RTS
Read/Write
31
DTR
Read/Write
User Output 2
’0’
’1’ = Drives OUT2N low
’0’ = Drives OUT2N high
User Output 1
’0’
’1’ = Drives OUT1N low
’0’ = Drives OUT1N high
Request To Send
’0’
’1’ = Drives RTSN low
’0’ = Drives RTSN high
Data Terminal Ready
’0’
’1’ = Drives DTRN low
’0’ = Drives DTRN high
Notes:
1. Reading these bits always return "000"
Line Status Register
This is an 8-bit write/read register as shown in Figure 10. The Line Status Register contains the current
status of receiver and transmitter. The bit definitions for the register are shown in Table 12. The offset
and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 10
Reserved
Error in RCVR FIFO THRE FE OE
0
23 24 25 26 27 28 29 30 31
Figure 10: Line Status Register (LSR)
TEMT BI
PE DR
Table 12: Line Status Register Bit Definitions
Bit
Name Access Reset Value
0-23
Reserved
N/A
N/A
Error in
24
RCVR Read/Write
’0’
FIFO
25
TEMT Read/Write
’1’
26
THRE Read/Write
’1’
27
BI
Read/Write
’0’
28
FE
Read/Write
’0’
Reserved
Description
Error in RCVR FIFO
RCVR FIFO contains at least one receiver error
Transmitter Empty
Transmitter Holding Register Empty
Break Interrupt
Set when SIN is held low for an entire character
time
Framing Error
Character missing a stop bit. Receiver
resynchronizes with next character, if possible
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DS577 April 18, 2007
Product Specification