XPS16550 Datasheet, PDF (12/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
FIFO Control Register⁽¹⁾
This is an 8-bit write/read register as shown in Figure 7. The FIFO Control Register contains the FIFO
configuration bits. The bit definitions for the register are shown in Table 9. The offset and accessibility
of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 7
Reserved
RCVR FIFO DMA Mode RCVR FIFO
Trigger Level Select
Reset
0
23 24 25 26 27 28 29 30 31
Figure 7: FIFO Control Register (FCR)
"00" XMTFIFOFIFOEN
Reset
Table 9: FIFO Control Register Bit Definitions⁽¹⁾
Bit
Name
Access Reset Value
0-23
Reserved
N/A
N/A
24-25
26-27
RCVR
FIFO
Trigger
Level
Read/Write
Reserved Read/Write
"00"
"00"⁽²⁾
28
DMA Mode
Select
Read/Write
’0’
29
XMIT FIFO
Reset
Read/Write
’0’
30
RCVR
FIFO Reset
Read/Write
’0’
31
FIFOEN Read/Write
’0’
1. FCR is not included in 16450 UART mode
2. Reading these bits always return "00"
Description
Reserved
RCVR FIFO Trigger Level.
"00" = 1 byte
"01" = 4 bytes
"10" = 8 bytes
"11" = 14 bytes
Always returns "00"
DMA Mode Select
’0’ = Mode 0
’1’ = Mode 1
Transmitter FIFO Reset
’1’ = Resets XMIT FIFO
Receiver FIFO Reset
’1’ = Resets RCVR FIFO
FIFO Enable
’1’ = Enables FIFOs
Line Control Register
This is an 8-bit write/read register as shown in Figure 8. The Line Control Register contains the serial
communication configuration bits. The bit definitions for the register are shown in Table 10. The offset
and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 8
Reserved
Stick
DLAB _Parity PEN
WLS
0
23 24 25 26 27 28 29 30 31
Figure 8: Line Control Register (LCR)
Set Break EPS STB
12
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DS577 April 18, 2007
Product Specification