XPS16550 Datasheet, PDF (13/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Table 10: Line Control Register Bit Definitions
Bit
Name
Access
Reset Value
0-23
Reserved
N/A
N/A
24
DLAB
Read/Write
’0’
25
Set Break Read/Write
’0’
26
Stick Parity Read/Write
’0’
27
EPS
Read/Write
’0’
28
PEN
Read/Write
’0’
29
STB
Read/Write
’0’
30-31
WLS
Read/Write
"00"
Description
Reserved
Divisor Latch Access Bit.
’1’ = Allows access to the Divisor Latch Registers
and reading of the FIFO Control Register
Set Break
’1’ = Sets SOUT to ’0’
Stick Parity
’1’ = When bits 28, 27 are logic1 the Parity bit is
transmitted and checked as a logic 0. If bit 28 is
a logic 0 then the Parity bit is transmitted and
checked as a logic 1.
’0’ = Stick Parity is disabled
Even Parity Select
’1’ = Selects Even parity
’0’ = Selects Odd parity
Parity Enable
’1’ = Enables parity
Number of Stop Bits
’0’ = 1 Stop bit
’1’ = 2 Stop bits or 1.5 if 5 bits/character selected
Word Length Select
"00" = 5 bits/character
"01" = 6 bits/character
"10" = 7bits/character
"11" = 8bits/character
Modem Control Register
This is an 8-bit write/read register as shown in Figure 9. The Modem Control Register contains the
modem signalling configuration bits. The bit definitions for the register are shown in Table 11. The
offset and accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 9
Reserved
"000"
Out2 RTS
0
23 24 25 26 27 28 29 30 31
Figure 9: Modem Control Register (MCR)
Loop Out1 _DTR
Table 11: Modem Control Register Bit Definitions
Bit
Name
Access
Reset Value
0-23
Reserved
N/A
N/A
24-26
N/A
Read/Write
"000"⁽¹⁾
27
Loop
Read/Write
’0’
Description
Reserved
Always "000"
Loop Back
’1’ = Enables loop back
DS577 April 18, 2007
www.xilinx.com
13
Product Specification