XPS16550 Datasheet, PDF (4/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
XPS 16550 UART I/O Signals
The XPS 16550 UART I/O signals are listed and described in Table 1.
Table 1: XPS 16550 UART I/O Signals
Port
Signal Name
Interface I/O
Initial
State
Description
System Signals
P1 Freeze
System
I
-
Freezes UART for software
debug (active high)
P2 IP2INTC_Irpt
System
O
Device interrupt output to
0
microprocessor interrupt input or
system interrupt controller
(active high)
P3 SPLB_Clk
System
I
-
PLB clock
P4 SPLB_Rst
System
I
-
PLB reset (active high)
PLB Master Interface Signals
P5
PLB_ABus[0 :
C_SPLB_AWIDTH-1]
PLB
I
-
PLB address bus
P6 PLB_PAValid
PLB
I
-
PLB primary address valid
indicator
P7
PLB_masterID[0 :
C_SPLB_MID_WIDTH - 1]
PLB
I
-
PLB current master identifier
P8 PLB_RNW
PLB
I
-
PLB read not write
P9
PLB_BE[0 : [C_SPLB_DWIDTH/8]
- 1]
PLB
I
-
PLB byte enables
P10 PLB_size[0 : 3]
PLB
I
-
PLB transfer size
P11 PLB_type[0 : 2]
PLB
I
-
PLB transfer type
P12
PLB_wrDBus[0 :
C_SPLB_DWIDTH - 1]
PLB
I
-
PLB write data bus
Unused PLB Master Interface Signals
P13 PLB_UABus[0 : 31]
PLB
I
-
PLB upper address bits
P14 PLB_SAValid
PLB
I
-
PLB secondary address valid
P15 PLB_rdPrim
PLB
I
-
PLB secondary to primary read
request indicator
P16 PLB_wrPrim
PLB
I
-
PLB secondary to primary write
request indicator
P17 PLB_abort
PLB
I
-
PLB abort bus request
P18 PLB_busLock
PLB
I
-
PLB bus lock
P19 PLB_MSize[0 : 1]
PLB
I
-
PLB data bus width indicator
P20 PLB_TAttribute[0 : 15]
PLB
I
-
PLB transfer attribute
P21 PLB_lockerr
PLB
I
-
PLB lock error
4
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DS577 April 18, 2007
Product Specification