XPS16550 Datasheet, PDF (11/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Table 7: Interrupt Enable Register Bit Definitions (Contd)
Bit
Name
Access Reset Value
Description
Enable Transmitter Holding Register Empty
Interrupt
30
ETBEI Read/Write
’0’
’0’ = Disables Transmitter Holding Register Empty
Interrupts
’1’ = Enables Transmitter Holding Register
Interrupts
Enable Received Data Available Interrupt
31
ERBFI Read/Write
’0’
’0’ = Disables Received Data Available Interrupts
’1’ = Enables Received Data Available Interrupts
Notes:
1. Reading these bits always return "0000"
Interrupt Identification Register
This is an 8-bit read register as shown in Figure 6. The Interrupt Identification Register contains the
priority interrupt identification. The bit definitions for the register are shown in Table 8. The offset and
accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 6
Reserved
FIFOEN "00" INTID2 INTPEND
0
23 24 25 26 27 28 29 30 31
Figure 6: Interrupt Identification Register (IIR)
Table 8: Interrupt Identification Register Bit Definitions
Bit
Name Access Reset Value
Description
0-23
24-25
26-27
Reserved
FIFOEN⁽³⁾
N/A
N/A
Read
Read
N/A
"00"
"00"⁽¹⁾
Reserved
FIFOs Enabled. Always zero if not in FIFO mode
Always returns "00"
28⁽³⁾-30
INTID2
Read
"000"
Interrupt ID
"011" = Receiver Line Status (Highest)
"010" = Received Data Available (Second)
"110" = Character Timeout (Second)
"001" = Transmitter Holding Register Empty (Third)
"000" = Modem Status (Fourth)
31
INTPEND⁽²⁾ Read
’1’
Interrupt Pending. Interrupt is pending when
cleared
Notes:
1. Reading these bits always return "00"
2. If INTPEND = ’0’, interrupt is pending. See National Semiconductor PC16550D data sheet for more detail
3. Bits are always zero in 16450 UART mode
DS577 April 18, 2007
www.xilinx.com
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Product Specification