XPS16550 Datasheet, PDF (7/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
utilizes only the resources required by the system and runs at the best possible performance. the
features that are parameterizable in the XPS 16550 UART core are as shown in Table 2.
Table 2: Design Parameters
Generic
Parameter
Description
Parameter Name
Allowable Values
Default VHDL
Value Type
System Parameters
G1 XILINX FPGA Family C_FAMILY
spartan3e, spartan3,
spartan3a,
spartan3an, virtex4,
virtex5
virtex5 string
PLB Parameters
G2
XPS 16550 UART Base
Address
C_BASEADDR
Valid Word Aligned
Address⁽¹⁾
None⁽²⁾
std_logi
c_vector
G3
XPS 16550 UART High
Address
C_HIGHADDR
C_HIGHADDR
-C_BASEADDR must be
a power of 2 >= to
C_BASEADDR+1FFF⁽¹⁾
None⁽²⁾
std_logi
c_vector
G4 PLB Data Bus Width C_SPLB_DWIDTH
32, 64, 128
32
integer
G5
PLB Address Bus
Width
C_SPLB_AWIDTH
32
32
integer
G6
PLB Point-to-Point or
shared topology
C_SPLB_P2P
0 : PLB shared topology
0
1 : Reserved
integer
G7
PLB master ID bus
width
C_SPLB_MID_WIDT
H
log₂(C_SPLB_NUM_MA
STERS) with a minimum
value of 1
3
integer
G8
Number of PLB
masters
C_SPLB_NUM_MAST
ERS
1 - 16
8
integer
G9
Width of slave data bus
C_SPLB_NATIVE_D
WIDTH
32
32
integer
G10 Burst support
C_SPLB_SUPPORTS
_BURST
0
0
integer
16550 UART Interface
G11 External xin
C_HAS_EXTERNAL_
XIN
0 : xin is open
1 : xin is driven by
SPLB_Clk
0
integer
G12 External rclk
C_HAS_EXTERNAL_
RCLK
0 : rclk is open
1 : rclk is driven by
baudoutN
0
integer
G13
Select 16450/16550
UART
C_IS_A_16550
0 : 16450 mode
1 : 16550 mode
1
integer
Notes:
1. Address range specified by C_BASEADDR and C_HIGHADDR must be at least 0x2000 and must
be a power of 2.
2. No default value will be specified to insure that the actual value is set, i.e. if the value is not set, a
compiler error will be generated.
DS577 April 18, 2007
www.xilinx.com
7
Product Specification