XPS16550 Datasheet, PDF (10/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Table 5: Receiver Buffer Register Bit Definitions
Bit
Name Access Reset Value
0-23
Reserved
N/A
N/A
24-31
RBR
Read
"00000000"
Description
Reserved. Set to zeroes on read
Last received character
Transmitter Holding Register
This is an 8-bit write register as shown in Figure 4. The Transmitter Holding Register contains the
character to be transmitted next. The bit definitions for the register are shown in Table 6. The offset and
accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 4
Reserved
THR
0
23 24 25 26 27 28 29 30 31
Figure 4: Transmit Holding Register (THR)
Table 6: Transmitter Holding Register Bit Definitions
Bit
Name Access
Reset
Value
0-23
Reserved
N/A
N/A
24-31
THR
Write
"11111111"
Description
Reserved
Holds the character to be transmitted next
Interrupt Enable Register
This is an 8-bit read/write register as shown in Figure 5. The Interrupt Enable Register contains the bits
which enable interrupts. The bit definitions for the register are shown in Table 7. The offset and
accessibility of this register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 5
Reserved
EDSSI ETBEI
0
23 24 25 26 27 28 29 30 31
Figure 5: Interrupt Enable Register (IER)
ELSI ERBFI
Table 7: Interrupt Enable Register Bit Definitions
Bit
Name
Access Reset Value
0-23
24-27
Reserved
N/A
N/A
Read/Write
N/A
"0000"⁽¹⁾
28
EDSSI Read/Write
’0’
29
ELSI
Read/Write
’0’
Description
Reserved
Always returns "0000"
Enable Modem Status Interrupt
’0’ = Disables Modem Status Interrupts
’1’ = Enables Modem Status Interrupts
Enable Receiver Line Status Interrupt
’0’ = Disables Receiver Line Status Interrupts
’1’ = Enables Receiver Line Status Interrupts
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DS577 April 18, 2007
Product Specification