XPS16550 Datasheet, PDF (16/20 Pages) Xilinx, Inc – XPS 16550 UART

XPS 16550 UART (v1.00a)
Scratch Register
This is an 8-bit write/read register as shown in Figure 11. The Scratch Register can be used to hold user
data. The bit definitions for the register are shown in Table 14. The offset and accessibility of this
register from C_BASEADDR value is as shown in Table 4.
Figure Top x-ref 12
Reserved
Scratch
0
23 24 25 26 27 28 29 30 31
Figure 12: Scratch Register (SCR)
Table 14: Scratch Register Bit Definitions
Bit
Name Access Reset Value
0-23
Reserved
N/A
N/A
24-31
Scratch Read/Write
"00000000"
Description
Reserved
Hold the data temporarily
Divisor Latch (Least Significant Byte) Register
This is an 8-bit write/read register as shown in Figure 13. The Divisor Latch (Least Significant Byte)
Register holds the least significant byte of the baud rate generator counter. The bit definitions for the
register are shown in Table 15. The offset and accessibility of this register from C_BASEADDR value is
as shown in Table 4.
Figure Top x-ref 13
Reserved
DLL
0
23 24 25 26 27 28 29 30 31
Figure 13: Divisor Latch (Least Significant Byte) Register
Divisor Latch (Most Significant Byte) Register
Table 15: Divisor Latch (Least Significant Byte) Register Bit Definitions
Bit
Name Access Reset Value
Description
0-23
Reserved
N/A
N/A
Reserved
24-31
DLL
Read/Write
"00000000"
Divisor Latch Least Significant Byte
This is an 8-bit write/read register as shown in Figure 14. The Divisor Latch (Most Significant Byte)
Register holds the most significant byte of the baud rate generator counter. The bit definitions for the
register are shown in Table 16. The offset and accessibility of this register from C_BASEADDR value is
as shown in Table 4.
16
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DS577 April 18, 2007
Product Specification