XC4000 Datasheet, PDF (9/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays

CLB RAM Timing Characteristics
ADDRESS
T_WC
WRITE
T_AS
WRITE ENABLE
DATA IN
READ
T_ILO
X,Y OUTPUTS
VALID
READ, CLOCKING DATA INTO FLIP-FLOP
CLOCK
TICK
XQ,YQ OUTPUTS
VALID
(OLD)
T_WP
T_AH
T_DS
T_DH
REQUIRED
VALID
TCH
T_CKO
VALID
(NEW)
READ DURING WRITE
WRITE ENABLE
DATA IN
(stable during WE)
X,Y OUTPUTS
DATA IN
(changing during WE)
X,Y OUTPUTS
T_WP
T_DH
VALID
T_WO
VALID
OLD
T_WO
T_DO
VALID
(PREVIOUS)
VALID
(OLD)
NEW
VALID
(NEW)
READ DURING WRITE, CLOCKING DATA INTO FLIP-FLOP
WRITE ENABLE
T_WP
T_WCK
T_DCK
DATA IN
CLOCK
XQ,YQ OUTPUTS
T_CKO
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