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XC4000 Datasheet, PDF (8/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays
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XC4000 Logic Cell Array Family
CLB Switching Characteristic Guidelines (continued)
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
CLB RAM Option
Speed Grade
-6
-5
-4
Description
Write Operation
Address write cycle time
Write Enable pulse width (High)
Address set-up time before beginning of WE
Address hold time after end of WE
DIN set-up time before end of WE
DIN hold time after end of WE
Symbol
Min Max Min Max Min Max Units
16 x 2 TWC
9.0
8.0
8.0
ns
32 x 1 TWCT
9.0
8.0
8.0
ns
16 x 2 TWP
5.0
4.0
4.0
ns
32 x 1 TWPT
5.0
4.0
4.0
ns
16 x 2 TAS
2.0
2.0
2.0
ns
32 x 1 TAST
2.0
2.0
2.0
ns
16 x 2 TAH
2.0
2.0
2.0
ns
32 x 1 TAHT
2.0
2.0
2.0
ns
16 x 2 TDS
4.0
4.0
4.0
ns
32 x 1 TDST
5.0
5.0
5.0
ns
both
TDHT
2.0
2.0
2.0
ns
Read Operation
Address read cycle time
Data valid after address change
(no Write Enable)
16 x 2
32 x 1
16 x 2
32 x 1
TRC
TRCT
TILO
TIHO
7.0
5.5
5.0
ns
10.0
7.5
7.0
ns
6.0
4.5
4.0 ns
8.0
7.0
6.0 ns
Read Operation, Clocking Data into Flip-Flop
Address setup time before clock K
Read During Write
Data valid after WE going active
(DIN stable before WE)
Data valid after DIN
(DIN change during WE)
16 x 2
32 x 1
16 x 2
32 x 1
16 x 2
32 x 1
TICK
TIHCK
TWO
TWOT
TDO
TDOT
6.0
4.5
4.5
ns
8.0
6.0
6.0
ns
12.0
10.0
9.0 ns
15.0
12.0
11.0 ns
11.0
9.0
8.5 ns
14.0
11.0
11.0 ns
Read During Write, Clocking Data into Flip-Flop
WE setup time before clock K
Data setup time before clock K
16 x 2 TWCK 12.0
10.0
9.5
ns
32 x 1 TWCKT 15.0
12.0
11.5
ns
16 x 2 TDCK 11.0
9.0
9.0
ns
32 x 1 TDCKT 14.0
11.0
11.0
ns
Note: Timing for the 16 x 1 RAM option is identical to 16 x 2 RAM timing
2-54
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