XC4000 Datasheet, PDF (3/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays

Wide Decoder Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Description
Speed Grade
Symbol
Device
-6
-5
-4
Max
Max
Max Units
Full length, both pull-ups,
inputs from IOB I-pins
T_WAF
XC4003
9.0
8.0
5.0
ns
XC4005
10.0
9.0
6.0
ns
XC4006
11.0
10.0
7.0
ns
XC4008
12.0
11.0
8.0
ns
XC4010
13.0
12.0
9.0
ns
XC4013
15.0
14.0
11.0
ns
XC4025
21.0
19.0
17.0
ns
Full length, both pull-ups
inputs from internal logic
T_WAFL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
11.0
7.0
ns
13.0
12.0
8.0
ns
14.0
13.0
9.0
ns
15.0
14.0
10.0
ns
16.0
15.0
11.0
ns
18.0
17.0
13.0
ns
24.0
23.0
20.0
ns
Half length, one pull-up
inputs from IOB I-pins
T_WAO
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
9.0
8.0
6.0
ns
10.0
9.0
7.0
ns
11.0
10.0
8.0
ns
12.0
11.0
9.0
ns
13.0
12.0
10.0
ns
15.0
14.0
12.0
ns
21.0
19.0
18.0
ns
Half length, one pull-up
inputs from internal logic
T_WAOL
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
12.0
11.0
8.0
ns
13.0
12.0
9.0
ns
14.0
13.0
10.0
ns
15.0
14.0
11.0
ns
16.0
15.0
12.0
ns
18.0
17.0
14.0
ns
24.0
23.0
21.0
ns
Note: These delays are specified from the decoder input to the decoder output. For pin-to-pin delays, add the input delay (T_PID)
and output delay (T_OPF or T_OPS), as listed on page 2-52.
PRELIMINARY
2-49