XC4000 Datasheet, PDF (6/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays

XC4000 Logic Cell Array Family
IOB Switching Characteristic Guidelines
Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%
functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing
patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more
precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.
Speed Grade
-6
Description
Symbol Min Max
Input
Propagation Delays
Pad to I1, I2
Pad to I1, I2, via transparent latch (no delay)
Pad to I1, I2, via transparent latch (with delay)
Clock (IK) toI1, I2, (flip-flop)
Clock (IK) to I1, I2 (latch enable, active Low)
T_PID
T_PLI
T_PDLI
T_IKRI
T_IKLI
4.0
8.0
26.0
8.0
8.0
Set-up Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
T_PICK
T_PICKD
7.0
25.0
Hold Time (Note 3)
Pad to Clock (IK), no delay
Pad to Clock (IK) with delay
T_IKPI
1.0
T_IKPID
neg
Output
Propagation Delays
Clock (OK) to Pad (fast)
same
(slew rate limited)
Output (O) to Pad (fast)
same
(slew-rate limited)
3-state to Pad begin hi-Z (slew-rate independent)
3-state to Pad active and valid (fast)
same
(slew -rate limited)
T_OKPOF
T_OKPOS
T_OPF
T_OPS
T_TSHZ
T_TSONF
T_TSONS
7.5
11.5
9.0
13.0
9.0
13.0
17.0
Set-up and Hold Times
Output (O) to clock (OK) set-up time
Output (O) to clock (OK) hold time
T_OOK
8.0
T_OKO
0
Clock
Clock High or Low time
T_CH/T_CL
5.0
Global Set/Reset
Delay from GSR net through Q to I1, I2
Delay from GSR net to Pad
GSR width*
T_RRI
T_RPO
T_MRW
14.5
18.0
21.0
-5
-4
Min Max Min Max Units
3.0
2.8 ns
7.0
6.0 ns
24.0
** ns
7.0
6.0 ns
7.0
6.0 ns
6.0
4.0
ns
24.0
**
ns
1.0
1.0
ns
neg
neg
ns
7.0
6.5 ns
10.0
9.5 ns
7.0
5.5 ns
10.0
8.5 ns
7.0
6.5 ns
10.0
9.5 ns
13.0
12.5 ns
6.0
5.5
ns
0
0
ns
4.5
4.0
ns
13.5
13.5 ns
17.0
14.0 ns
18.0
18.0
ns
* Timing is based on the XC4005. For other devices see XACT timing calculator.
** See preceding page
Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). Slew rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times. For the effect of capacitive loads on
ground bounce, see pages 8-8 through 8-10.
2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the
internal pull-up or pull-down resistor or alternatively configured as a driven output or be driven from an external source.
3. Input pad setup times and hold times are specified with respect to the internal clock (IK). To calculate system setup time,
subtract clock delay (clock pad to IK) from the specified input pad setup time value, but do not subtract below zero.
Negative hold time means that the delay in the input data is adequate for the external system hold time to be zero,
provided the input clock uses the Global signal distribution from pad to IK.
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