XC4000 Datasheet, PDF (2/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays

XC4000 Logic Cell Array Family
Absolute Maximum Ratings
Symbol Description
Units
V_CC Supply voltage relative to GND
–0.5 to +7.0
V
V_IN
Input voltage with respect to GND
–0.5 to V_CC +0.5
V
V_TS Voltage applied to 3-state output
–0.5 to V_CC +0.5
V
T_STG Storage temperature (ambient)
–65 to + 150
°C
T_SOL Maximum soldering temperature (10 s @ 1/16 in. = 1.5 mm)
+ 260
°C
T_J
Junction temperature
+ 150
°C
Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.
These are stress ratings only, and functional operation of the device at these or any other conditions beyond
those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings
conditions for extended periods of time may affect device reliability.
Operating Conditions
Symbol Description
Min Max Units
V_CC
Supply voltage relative to GND Commercial 0°C to 85°C junction
4.75 5.25 V
Supply voltage relative to GND Industrial -40°C to 100°C junction
4.5 5.5
V
Supply voltage relative to GND Military –55°C to 125°C case
4.5 5.5
V
V_IH
High-level input voltage (XC4000 has TTL-like input thresholds)
2.0 V_CC
V
V_IL
Low-level input voltage (XC4000 has TTL-like input thresholds)
0
0.8 V
T_IN
Input signal transition time
250 ns
At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
DC Characteristics Over Operating Conditions
Symbol Description
Min Max Units
V_OH
High-level output voltage @ I_OH = –4.0 mA, V_CC min
V_OL
Low-level output voltage @ I_OL = 12.0 mA, V_CC min (Note 1)
I_CCO
Quiescent LCA supply current (Note 2)
I_IL
Leakage current
C_IN
Input capacitance (sample tested)
I_RIN
Pad pull-up (when selected) @ V_IN = 0V (sample tested)
I_RLL
Horizontal Long Line pull-up (when selected) @ logic Low
2.4
V
0.4 V
10
mA
–10 +10
µA
15
pF
0.02 0.25 mA
0.2 2.5 mA
Note: 1. With 50% of the outputs simultaneously sinking 12 mA.
2. With no output current loads, no active input or longline pull-up resistors, all package pins at V_CC or GND, and
the LCA configured with a MakeBits tie option.
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