XC4000 Datasheet, PDF (5/22 Pages) Xilinx, Inc – Third Generation Field-Programmable Gate Arrays

Guaranteed Input and Output Parameters (Pin-to-Pin)
All values listed below are tested directly, and guaranteed over the operating conditions. The same parameters can also be derived
indirectly from the IOB and Global Buffer specifications. The XACT delay calculator uses this indirect method. When there is a
discrepancy between these two methods, the values listed below should be used, and the derived values must be ignored.
Description
Global Clock to Output (fast) using OFF
T_PG
OFF
.....
Global Clock-to-Output Delay
X3202
Global Clock to Output (slew limited) using OFF
T_PG
OFF
Global Clock-to-Output Delay
Input Set-up Time, using IFF (no delay)
Input
Set-Up
&
Hold
Time
D
T_PG
IFF
X3201
Input Hold time, using IFF (no delay)
.....
X3202
Input
Set-Up
&
Hold
Time
D
T_PG
IFF
X3201
Input Set-up Time, using IFF (with delay)
Input
Set-Up
&
Hold
Time
D
T_PG
IFF
X3201
Input Hold Time, using IFF (with delay)
Input
Set-Up
&
Hold
Time
D
T_PG
IFF
X3201
Speed Grade
Symbol
Device
T_ICKOF
(Max)
T_ICKO
(Max)
T_PSUF
(Min)
T_PHF
(Min)
T_PSU
(Min)
T_PH
(Min)
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
XC4003
XC4005
XC4006
XC4008
XC4010
XC4013
XC4025
-6
-5
15.1
12.5
15.5
13.0
15.7
13.2
16.1
13.6
16.5
14.0
17.5
15.0
25.5
22.0
19.9
15.2
20.5
16.0
20.7
16.2
21.1
16.6
21.5
17.0
22.5
18.0
29.5
25.0
2.4
2.0
2.0
1.5
1.8
1.3
1.4
0.9
1.0
0.5
0.5
0
0
0
5.1
4.0
5.5
4.5
5.7
4.7
6.1
5.1
6.5
5.5
7.5
6.5
18.0
16.0
21.5
18.5
21.0
18.0
20.8
17.8
20.4
17.4
20.0
17.0
19.0
16.0
18.0
15.0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
-4
Units
11.6
ns
12.0
ns
12.2
ns
12.6
ns
13.0
ns
14.0
ns
21.0
ns
14.4
ns
15.0
ns
15.2
ns
15.6
ns
16.0
ns
17.0
ns
24.0
ns
1.6
ns
1.2
ns
1.0
ns
0.6
ns
0.2
ns
0
ns
0
ns
4.0
ns
4.5
ns
4.7
ns
5.1
ns
5.5
ns
6.5
ns
15.5
ns
12.0
ns
12.0
ns
12.0
ns
12.0
ns
12.0
ns
12.0
ns
12.0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
0
ns
Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). When testing fast outputs, only one
output switches. When testing slew-rate limited outputs, half the number of outputs on one side of the device are switching. These
parameter values are tested and guaranteed for worst-case conditions of supply voltage and temperature, and also with the most
unfavorable clock polarity choice.
T_PDLI for -4 Speed Grade
Pad to I1, I2
via transparent
latch, with delay
XC4003 17.6 ns
XC4005 17.9 ns
XC4006 18.0 ns
XC4008 18.3 ns
XC4010 18.6 ns
XC4013 19.3 ns
XC4025 23.5 ns
PRELIMINARY
See page 2-52
T_PICKD for -4 Speed Grade
Input set-up time
pad to clock (IK)
with delay
XC4003 15.6 ns
XC4005 15.9 ns
XC4006 16.0 ns
XC4008 16.3 ns
XC4010 16.6 ns
XC4013 17.3 ns
XC4025 22.5 ns
X6082
2-51