DS634 Datasheet, PDF (9/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
The latency in microseconds is defined as in Equation 2:
Latency = ----^L-----
fclk
Equation 2
where L is the latency in terms of number of clocks and f_clk is the system clock frequency in MHz.
Table 3 shows the latency of the IEEE 802.16e CTC decoder core in μs for all the block sizes versus num-
ber of full iterations and clock frequency when the number of SISOs is two. Table 4 shows the latency of
the IEEE 802.16e CTC decoder core in μs for all the block sizes versus number of full iterations and clock
frequency when the number of SISOs is four. Table 5 shows the latency of the IEEE 802.16e CTC
Ddecoder core in μs for all the block sizes versus number of full iterations and clock frequency when the
number of SISOs is five. The numbers are based on the above two equations. In general, for a fixed
number of iterations, latency is reduced by using more SISOs and higher system clock frequencies.
is_{Table 3: Latency of the IEEE 802.16e CTC Decoder Core Using Two SISOs}
Data
c^Block
Size (N)
fclk = 160 MHz
Latency
Latency
(µs) Ni = 4 (µs) Ni = 5
fclk = 190 MHz
Latency
Latency
(µs) Ni = 4 (µs) Ni = 5
fclk = 215 MHz
Latency Latency (µs)
(µs) Ni = 4
Ni = 5
o ²⁴
3.61
4.47
3.04
3.76
2.68
3.33
36
4.81
5.97
4.05
5.03
3.58
4.44
n 48
6.01
7.47
5.06
6.29
4.47
5.56
72
8.41
10.47
7.08
8.82
6.26
7.79
t 96
10.81
13.47
9.10
11.34
8.04
10.02
i 108
12.01
14.97
10.11
12.61
8.93
11.14
n ₁₂₀
13.21
16.47
11.12
13.87
9.83
12.26
144
15.61
19.47
13.14
16.39
11.61
14.49
u ₁₈₀
19.21
23.97
16.17
20.18
14.29
17.84
192
20.41
25.47
17.18
21.45
15.19
18.95
e ₂₁₆
22.81
28.47
19.21
23.97
16.97
21.19
240
25.21
31.47
21.23
26.50
18.76
23.42
d ₄₈₀
25.21
31.47
21.23
26.50
18.76
23.42
960
49.21
61.47
41.44
51.76
36.62
45.74
1440
73.21
91.47
61.65
77.03
54.48
68.07
IP ₁₉₂₀
97.21
121.47
81.86
102.29
72.34
90.40
2400
121.21
151.47
102.07
127.55
90.20
112.72
DS634 December 2, 2009
www.xilinx.com
9
Product Specification