DS634 Datasheet, PDF (16/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
Table 12: Resource Utilization when the Largest Block Size is 240 Pairs (60 Bytes) Targeting
a Virtex-5 FPGA
Number of
SISOs
I/Os
LUTs
18k or 36k
FFs
Slices
Block
DSP48s
RAMs
1
107
3,369
3,638
1,089
9 or 5
2
2
107
6,611
6,767
2,008
18 or 9
4
3
107
9,839
9,891
2,886
27 or 14
6
D₄
107
13,063
12,945
3,948
36 or18
8
5
107
16,325
16,133
5,166
45 or 23
10
6
107
19,549
19,158
5,533
54 or 27
12
is₈
107
26,034
25,490
7,748
72 or 36
16
c^{Table 13: IEEE 802.16 CTC Decoder Core Static Timing Results Targeting a Virtex-4 FPGA}
Xilinx FPGA
Clock Speed (MHz)
o_{XC4VLX60 -10}
162.443
XC4VLX60 -11
191.132
n_{XC4VLX60 -12}
216.029
t Table 14: IEEE 802.16 CTC Decoder Core Static Timing Results Targeting a Virtex-5 FPGA
i Xilinx FPGA
Clock Speed (MHz)
n _{XC5VLX85 -1}
196.040
XC5VLX85 -2
225.327
u _{XC5VLX85 -3}
245.459
e _{Table 15: IEEE 802.16e CTC Decoder Core Static Timing results Targeting a Virtex-6 FPGA}
(PREVIEW 0.63 2009-04-27)
d ^{Xilinx FPGA}
Clock Speed (MHz)
XC6VLX75T-1
225.683
XC6VLX75T-2
255.102
IP XC6VLX75T-3
286.041
Table 16: IEEE 802.16e CTC Decoder Core Static Timing results Targeting a Spartan-6 FPGA
Xilinx FPGA
Clock Speed (MHz)
XC6SLX45T-2
111.161
16
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DS634 December 2, 2009
Product Specification