DS634 Datasheet, PDF (4/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
decoder 2. Similarly, a single circuit is used to perform both the interleaving and de-interleaving func-
tions for the extrinsics.
Although there is a factor of two savings in hardware by sharing resources between half iterations, the
implementation of each decoder has a P-fold complexity increase over that shown in Figure 3. In par-
ticular, to increase data throughput, P SISO processors are used to process the data on each half itera-
tion. This is accomplished by processing the same data block by different SISO processors for the 480,
960, 1440, 1920 and 2400 blocks and by processing different data blocks by different SISO processors for
the remaining blocks.
The decoder implementation contains an input buffer that allows new code blocks to be written while
Dstill processing the previous code blocks (that is, double buffered). The input buffer stores the channel
data in a set of P memories that are independently accessed by P SISO processors. During the inter-
leaved iteration, systematic data is read in an interleaved fashion, while parity data is read in a non-
i_{interleaved fashion. During the non-interleaved iteration, the systematic and parity data are both read}
s_{in a non-interleaved fashion.}
In addition to an input buffer, the core also contains an output buffer. At the end of the final iteration,
c_{soft decoded data is written independently to the output buffer by all P SISOs. The soft decoded data}
stored in the output buffer drives the core output. Like the input buffer, the output buffer contains two
o _{pages of memory so that soft decoded data from new code blocks can be written while data from the}
previous code blocks is still being read.
n _{CTC Decoder Interface}
t ^{A block diagram of the CTC decoder core interface is shown in Figure 4. The port definitions are given}
in Table 1.
i _{X-Ref Target - Figure 4}
n_{earlyterm[1:0]}
Ncode[11:0]
u ^NumIter[7:0]
ex_scale[7:0]
Adata_in[widthd-1:0]
Bdata_in[widthd-1:0]
e _{Y1data_in[widthd-1:0]}
Y2data_in[widthd-1:0]
W1data_in[widthd-1:0]
d ^{W2data_in[widthd-1:0]}
EX1data_in[widthe-1:0]
EX2data_in[widthe-1:0]
data_en
start_in
I ^clk
P ^reset
Adata_out[widthd-1:0]
Bdata_out[widthd-1:0]
EX1data_out[widthe-1:0]
EX2data_out[widthe-1:0]
dataout_valid
start_out
rdyforblk[1:0]
overflow
ds137_04_041006
Figure 4: CTC Decoder Core Interface Signals
4
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DS634 December 2, 2009
Product Specification