DS634 Datasheet, PDF (1/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
DS634 December 2, 2009
Product Specification
Introduction
The IEEE 802.16e CTC decoder core performs iterative
decoding of channel data that has been encoded as
described in Section 8.4.9.2.3 of the IEEE Std 802.16e-2005
specification and corrigendum IEEE P802.16Rev2/D0b
D_{(June 2007). The IEEE 802.16e code is a parallel concate-}
nated convolutional code with an input data block of 2N
bits. Through parallel processing with parameterizable
i^{number of SISOs, this LogiCORE™ IP decoder core is}
s ^{capable of achieving high throughput. The decoded data}
rate reaches up to 220 Mbps with five iterations using
eight SISOs at 286 MHz clock frequency.
c _Features
o _{• Supports Virtex®-6, Virtex-5, Virtex-4, Spartan®-6,}
Spartan-3, Spartan-3E, and Spartan-3A DSP FPGA
families
n • Supports all interleaver block sizes of the CTC
OFDMA PHY mode including the HARQ and IR
t HARQ modes: 24, 36, 48, 72, 96, 108, 120, 144, 180,
i ^{192, 216, 240, 480, 960, 1440, 1920, and 2400 pairs}
n • Performs parallel processing with parameterizable
number of SISOs to achieve high throughput and
reduce latency
u • Supports dynamic block size switching without
interruption
e • Programmable number of iterations dynamically
changeable per block
• Adaptive rate change via puncturing interface
d • Uses MAX-LOG-MAP algorithm with extrinsic
scaling
• Parameterizable options for soft data input and
IP extrinsic bits
• Latency depends on block size and varies between
5 μs to 76 μs when targeting Virtex-4, between 4 μs
to 63 μs when targeting Virtex-5, and between 4 μs
to 55 μs when targeting Virtex-6 (slowest speed
grade, five iterations, and four SISO option)
• Fully synchronous design with single clock
domain
• Double-buffered input to accommodate burst or
continuous data
• Available using the CORE Generator™ v11.2
software, which is included with the ISE® 11.2
software
Functional Description
The IEEE 802.16e code is a parallel concatenated convo-
lutional code as illustrated in Figure 1. The input data
block contains 2N bits. The input data is split into even
and odd samples (A and B, each of length N bits) and is
fed to the first constituent encoder. The constituent
encoder is a double binary Circular Recursive System-
atic Convolutional (CRSC) encoder that creates two
parity bits, Y₁ and W₁, for every pair of input bits, A
and B. The input bits are passed to the output to form
the systematic symbols as shown in Figure 1.
Prior to encoding with the second constituent encoder,
the input data is interleaved with the interleaver
described in Section 8.4 of the specification. The inter-
leaved data is fed to a second constituent encoder that
is identical to the first one. The second constituent
encoder creates two parity bits, Y₂ and W₂, for every
pair of the interleaved input bits. The systematic bits
• Clock speed exceeds 162 MHz in Virtex-4 speed
are not transmitted from the second constituent
grade -10, 196 MHz in Virtex-5 speed grade -1, and _encoder.
225 MHz in Virtex-6 speed grade -1
• Decoded data rate depends on block size and
varies between 44 Mbps to 63 Mbps when
targeting Virtex-4, between 53 Mbps to 76 Mbps
The definition of the CRSC encoder is shown in
Figure 2. Each CRSC encoder is initialized to the circu-
lation state at the beginning of every input block. The
when targeting Virtex-5, and between 61 Mbps to
88 Mbps when targeting Virtex-6 (slowest speed
grade, five iterations, and four SISO options)
circulation state is calculated as described in Section 8.4
of the specification.
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DS634 December 2, 2009
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Product Specification