DS634 Datasheet, PDF (5/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
Table 1: Core Port Definitions
Signal
Direction
Description
earlyterm
Input
Early termination enable signal. When 00, early termination is disabled (the
iterative process stops after a number of iterations given by NumIter), when
01 early termination scheme1 is enabled (comparing hard decisions over
Ncode
NumIter
D^ex_scale
Adata_in
i_{Bdata_in}
s_{Y1data_in}
Y2data_in
c_{W1data_in}
W2data_in
o _{EX1data_in}
EX2data_in
n _{data_en}
t _{start_in}
in _clk
reset
u ^Adata_out
Bdata_out
EX1data_out
e _{EX2data_out}
dataout_valid
d _{start_out}
IP _rdyforblk
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Output
two successive iterations), and when 10, early termination scheme2 is
enabled (comparing hard decisions over three successive iterations).
Data block length N in pairs.
Number of full iterations.
Extrinsic scaling. The extrinsic data is scaled by a fractional number.
Therefore, the input signal ex_scale is equal to 256 multiplies by that
fractional number.
First received non-interleaved systematic data.
Second received non-interleaved systematic data.
First received non-interleaved parity data.
First received interleaved parity data.
Second received non-interleaved parity data.
Second received interleaved parity data.
First received extrinsic data.
Second received extrinsic data.
Data input enable. The input data is clocked into the core on the rising edge
of clk when data_en = 1.
Marks the start of an input code block. Must pulse High with the first data_en
of a new code block.
Data input clock. Core is clocked on the rising edge of clk.
Active high synchronous reset.
First output data.
Second output data.
First extrinsic output data.
Second extrinsic output data.
High when the Adata_out and Bdata_out signals contain valid data. Used as
an enable signal for downstream processing of the Adata_out and Bdata_out
signals.
Marks the start of a decoded output block. Pulses High with the start of a new
output block.
This signal is High when the decoder is ready for a new input block. If this
signal is Low, the decoder is not ready for another input block. Pulsing
start_in High when this signal is Low corrupts the operation of the core. Bit
one controls the flow of the 480, 960, 1440, 1920, and 2400 blocks, while bit
zero controls the flow of the remaining blocks.
overflow
Output
Input buffer overflow signal. This signal goes High when the start_in signal
goes High while the rdyforblk signal is still Low.
DS634 December 2, 2009
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Product Specification