DS634 Datasheet, PDF (11/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
Table 5: Latency of the IEEE 802.16e CTC Decoder Core Using Five SISOs (Cont’d)
Data
Block
Size (N)
fclk = 160 MHz
Latency
Latency
(µs) Ni = 4 (µs) Ni = 5
fclk = 190 MHz
Latency
Latency
(µs) Ni = 4 (µs) Ni = 5
fclk = 215 MHz
Latency Latency (µs)
(µs) Ni = 4
Ni = 5
240
25.21
31.47
21.23
26.50
18.76
23.42
480
960
1440
D 1920
2400
10.81
20.41
30.01
39.61
49.21
13.47
25.47
37.47
49.47
61.47
9.10
17.18
25.27
33.35
41.44
11.34
21.45
31.55
41.66
51.76
8.04
15.19
22.33
29.47
36.62
10.02
18.95
27.88
36.81
45.74
i_{Decoded Information Data Rate}
s_{The achievable information bit rate (Rb) in Mbps of the IEEE 802.16e CTC decoder core is given by}
Equation 3.
c _Rb
=
Ns _⎝⎛ ²---_L-^N---_′--^′--
⎞
⎠
fcl
k
o _{Equation 3}
where N_s is the number of SISOs, N' is the block size in pairs (N) divided by the number of SISOs when
n _{N is equal to 480, 960, 1440, 1920, or 2400 pairs; otherwise, N' is the block size in pairs (N), fclk is the sys-}
tem clock frequency in MHz, and L^’ is latency of the decoder from the time the last sample of the first
code block is written into the input buffer to the time the last sample of the first code block is written
t _{into the output buffer. Latency for the CTC decoder core is given by Equation 4.}
in_{L′ = 2Ni[2N' + C] + 12}
Equation 4
u _{where Ni is the number of iterations, N' is the data block size in pairs (N) divided by the number of}
SISOs (Ns), when N is equal to 480, 960, 1440, 1920, or 2400 pairs; otherwise, N' is the block size in pairs
(N), and C is a constant that is equal to 21 when early termination is disabled; otherwise C is equal to 25.
e _{Table 6 shows the decoded information bit rate of the IEEE 802.16e CTC decoder core in Mbps for all}
block sizes versus number of full iterations and clock frequency when the number of SISOs is two.
d _{Table 7 shows the decoded information bit rate of the IEEE 802.16e CTC decoder core in Mbps for all}
block sizes versus number of full iterations and clock frequency when the number of SISOs is four.
Table 8 shows the decoded information bit rate of the IEEE 802.16e CTC decoder core in Mbps for all
I ^{block sizes versus number of full iterations and clock frequency when the number of SISOs is five.The}
P ^{numbers are based on Equation 3 and Equation 4. In general, for a fixed number of iterations, the}
decoded information bit rate is increased by using more SISOs and higher system clock frequencies.
Table 6: Decoded Data Rate of the IEEE 802.16e CTC Decoder Core Using Two SISOs
Data Block
Size (N)
24
fclk = 160 MHz
R_b
(Mbps)
N_i = 4
27.23
R_b
(Mbps)
N_i = 5
21.88
fclk = 190 MHz
R_b
(Mbps)
N_i = 4
32.34
R_b
(Mbps)
N_i = 5
25.98
fclk = 215 MHz
R_b
(Mbps)
N_i = 4
36.60
R_b
(Mbps)
N_i = 5
29.40
36
30.48
24.46
36.19
29.04
40.95
32.87
DS634 December 2, 2009
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Product Specification