DS634 Datasheet, PDF (3/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
X-Ref Target - Figure 3
ex ₂ ex ₁
A
B
SISO
A0
Y1
W1
D _Interleaver
is _A'
B'
c^Y2
on ^W2
Decoder 1
B0
ex ₂ ex ₁
Interleaver
ex'2 ex'1
SISO
Decoder 2
ex'2 ex'1
Deinterleaver
ti _{ds137_03_061005}
n _{Figure 3: Block Diagram of CTC Decoding Algorithm}
In addition to using the channel data, each SISO decoder uses extrinsic information from the other
u _{decoder to update its own extrinsic information output. The extrinsic information from SISO decoder 1}
must be interleaved before being processed by SISO decoder 2. Similarly, the extrinsic information from
SISO decoder 2 must be de-interleaved before being processed by SISO decoder 1. A half iteration
e _{occurs every time a single decoder finishes generating new extrinsics. A full iteration contains two half}
iterations.
d _{The order in which decoding begins is somewhat arbitrary, but there are some practical advantages to}
starting with the interleaved data. In particular, by starting with SISO decoder 2, a full iteration occurs
when decoder 1 has finished updating its output. The estimated information bit sequences, A₀ and B₀,
I ^{from decoder 1 is in non-interleaved order. In contrast, by starting with decoder 1, the full iteration}
P ^{ends with decoder 2, and the estimated bit sequences, A`0 and B`0, must be de-interleaved before being}
processed downstream.
Another practical consideration in choosing the decode order has to do with the nature of the channel.
In an Additive White Gaussian Noise (AWGN) channel, the order of the decoding should have no
impact on Bit Error Rate (BER) performance. However, in a fading channel, the first half iteration
should have some advantage if it is based on the interleaved data. For these reasons, the IEEE 802.16e
CTC decoder core processes the interleaved data on the first half iteration.
It should be noted that the actual implementation of the decoding algorithm is different than what is
indicated in Figure 3. For example, the SISO decoder is time shared between the two half iterations.
Therefore, the hardware that implements SISO decoder 1 is the same hardware that implements SISO
DS634 December 2, 2009
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Product Specification