DS634 Datasheet, PDF (17/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
Design Verification
The decoder core was verified through VHDL simulation and hardware testing. Self-checking VHDL
test benches were written for many of the design submodules. For example, the SISO design was veri-
fied by comparing the output of the VHDL SISO model to that of a bit-true MATLAB® model of the
SISO with the same stimulus.
In addition to verifying the function of each subdesign, the top-level decoder design was also verified
with a self-checking test bench. The bit-true MATLAB model was used to generate files of input stimu-
lus and the corresponding output vectors. The input stimulus was read by the top-level test bench and
Dapplied to the decoder core. The resulting output of the decoder core was then compared to the MAT-
LAB model output vectors read from a file.
Hardware testing of the decoder core was performed using the ML402 Prototyping Board populated
i^{with an XC4VSX35 -10 device. A hardware test bench was developed to test the BER performance of the}
s^{decoder. In addition to the decoder core, the hardware test bench contains an LFSR-based data genera-}
tor, the Xilinx IEEE 802.16e CTC Encoder core and the Xilinx AWGN core. It also contains other cir-
c^{cuitry required to make BER measurements, such as an adder, a bit counter, and an error counter. A}
simplified block diagram of the hardware test bench is shown in Figure 9.
o ^{In addition to the previously mentioned circuitry, the hardware test bench also contains a block that}
quantizes the signal plus noise data into the 6-bit two’s complement data expected by the decoder. The
data signal is assumed to be normalized to ±1. The quantization circuit scales the signal plus noise data
n _{by 8 (3 fractional bits), rounds the scaled data to the nearest integer, then hard limits to ±31 (6 total bits).}
X-Ref Target - Figure 9
X-Ref Target - Figure 9
t _Info
i _Source
IEEE 802.16e
CTC
Encoder
AWGN
Channel
IEEE 802.16e
CTC
Decoder
BER
Circuitry
n _{Figure 9: Block Diagram of Hardware Test Bench}
ds137_07_0521207
u _{Speed and Power Consumption Measurements}
e _{Speed and power consumption measurements of the CTC decoder core were performed using the}
Virtex-5 FF676 FPGA AFX Prototyping Board populated with an XC5VLX50 -1 device. The same hard-
d ^{ware test bench described in the design verification section was used to measure speed and power con-}
sumption of the CTC decoder core. Table 17 shows the dynamic power consumption versus number of
full iterations when running the CTC decoder core at 49 Mbps using 196 MHz clock. Table 18 shows the
dynamic power consumption versus number of full iterations when running the CTC decoder core at
IP _{maximum decoding rate using 196 MHz clock. The dynamic power consumption is defined as the dif-}
ference in power consumption between the case where the entire test bench including the CTC decoder
core is enabled and the case where the test bench is enabled while the CTC decoder core is disabled.
Table 17: IEEE 802.16e CTC Decoder Core Power Consumption at Fixed Decoding Rate
Number of Iterations
Decoded Data Rate
Dynamic Power
Consumption (mW)
1
49
178
2
49
356
DS634 December 2, 2009
www.xilinx.com
17
Product Specification