DS634 Datasheet, PDF (18/20 Pages) –

IEEE 802.16e CTC Decoder v4.0
Table 17: IEEE 802.16e CTC Decoder Core Power Consumption at Fixed Decoding Rate
Number of Iterations
Decoded Data Rate
Dynamic Power
Consumption (mW)
3
49
536
4
49
717
5
49
897
Table 18: IEEE 802.16e CTC Decoder Core Power Consumption at Maximum Decoding Rate
D _{Number of Iterations}
Maximum
Decoded Data Rate
Dynamic Power
Consumption (mW)
4
93.61
1,350
i₅
74.93
1,351
s₆
62.47
1,350
c_{BER Performance}
All BER results were obtained using the hardware test bench described in "Design Verification." At the
o _{lower SNRs, the number of bit errors counted was generally over 4,000. At the higher SNRs, the mini-}
mum number of bit errors was over 1,000. The BER results were based on 6-bits input data (3 fractional
n ^{bits and 3 integer bits), 6-bits extrinsic, and 10-bits accumulated state metric. Figure 10 shows the BER}
performance of the IEEE 802.16e decoder core using rate 1/2 code and block size 240 pairs versus the
number of iterations. Figure 11 shows the BER performance of the IEEE 802.16e decoder core using rate
t _{1/3 code and block size 240 pairs versus the number of iterations.}
i _{X-Ref Target - Figure 10}
n _{IEEE 802.16e CTC Coding Performance}
u _1.00E+00
e ^1.00E-01
1.00E-02
d _1.00E-03
1.00E-04
IP ^1.00E-05
1 iteration
2 iterations
3 iterations
4 iterations
5 iterations
6 iterations
1.00E-06
7 iterations
1.00E-07
1.00E-08
1.00E-09
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
Eb/No (dB)
Figure 10: BER Performance of Rate 1/2 CTC Code with Block Size N = 240
18
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DS634 December 2, 2009
Product Specification