DS583 Datasheet, PDF (9/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Table 5: XPS System ACE Interface Controller Parameters (Cont’d)
Generic Feature/Description Parameter Name
Allowable
Values
Default VHDL
Value Type
G10
Selects the transactions as
being single beat or burst
C_SPLB_SUPPORT
_BURSTS
0 = Supports only
single beat
transactions
0
integer
System ACE Parameters
G11
System ACE MPU Data Bus
Access Mode ⁽²⁾
C_MEM_WIDTH
8, 16
16
integer
1. The range specified by C_BASEADDR and C_HIGHADDR must be sized and aligned to some power of 2, 2ⁿ .
Then, the n least significant bits of C_BASEADDR is zero. This range needs to encompass the addresses needed
by the XPS SYSACE registers
2. Please refer to Xilinx DS080, System ACE Compact Flash Solution, for more information
Allowable Parameter Combinations
The address-range size of the XPS System ACE Interface Controller must be a power of 2. If the desired
address-range size is represented by 2ⁿ, then the n least significant bits of the base address must be 0.
C_BASEADDR and C_HIGHADDR must specify an address range whose size is atleast 0x80, to cover
the addressable registers and data buffer available in the Xilinx System Ace Compact Flash chip.
XPS System ACE Interface Controller Parameter-Port Dependencies
The dependencies between the XPS System ACE Interface Controller design parameters and I/O
signals are described in Table 6. In addition, when certain features are parameterized out of the design,
the related logic will no longer be a part of the design. The unused input signals and related output
signals are set to a specified value.
Table 6: XPS System ACE Interface Controller Parameter-Port Dependencies
Generic
or Port
Parameter
Affects
Depends Relationship Description
Design Parameters
G4
C_SPLB_AWIDTH
P3
-
Width of the PLB Address Bus
G5
C_SPLB_DWIDTH
P7,
P10,
P33
-
Width of the PLB Data Bus
G7
C_SPLB_MID_DWIDTH
P5
G8
Width of Master ID Bus
G8
C_SPLB_NUM_MASTERS
P36,P37,
P38
-
The number of Master Devices
connected to PLB bus
G11 C_MEM_WIDTH
P49, P50, P51
-
Width of the System ACE Data
Bus
I/O Signals
P3
PLB_ABus
-
G4
Width varies with the width of the
PLB Address Bus
P5
PLB_MasterID
-
G7
Width varies with the MID width
P7
PLB_BE
-
G5
Width varies with the width of the
PLB Data Bus
P10 PLB_wrDBus
-
G5
Width varies with the width of the
PLB Data Bus
DS583 December 2, 2009
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Product Specification