DS583 Datasheet, PDF (4/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
X-Ref Target - Figure 2
Bus2IP_RdCE
Bus2IP_WrCE
Mem_A
Mem_DQ_O
Mem_DQ_T
Mem_DQ_I
IP2Bus_RdAck
IP2Bus_WrAck
SPLB_CLk
SYNC_2_CLKS
SysACE_MPA
SysACE_MPD_O
SysACE_MPD_T
SysACE_MPD_I
3-State Buffer
Added in
System
Generation
SysACE_Clk
valid_mem_t
MEM_STATE_MACHINE
SysACE_CEN
SysACE_OEN
SysACE_WEN
SysACE_Clk
Figure 2: System ACE Interface Controller Diagram
DS583_02_101509
The XPS System ACE Interface Controller core does not contain any internal registers or addressable
memory space, therefore the mapping of PLB address bus is one-to-one with the System ACE address
bus (SysACE_MPA) as shown in Table 1.
Table 1: PLB Address Bus to System ACE Address Bus Mapping (done in IP core)
PLB Address Bus
System ACE Address Bus
PLB_ABus[25 : 31]
SysACE_MPA[6 : 0]
The Xilinx System ACE Compact Flash chip is a true little-endian device and the PLB is a big-endian
bus. Therefore the XPS System ACE Interface Controller will do a bit-swap in each byte when
connecting the PLB data bus to the System ACE data bus as shown in Table 2.
Table 2: PLB Data Bus to System ACE Data Bus Mapping (done in IP core)
PLB Data Bus
System ACE Data Bus
PLB_DBus[8 : 15]
SysACE_MPD[15 : 8]
PLB_DBus[0 : 7]
SysACE_MPD[7 : 0]
Note however, that the XPS System ACE Interface Controller does not perform the byte swapping
necessary to interface to a little-endian device when configured to use 16-bit mode. Therefore, the
software drivers provided for this core will perform the necessary byte-swapping to correctly interface
to the Xilinx System ACE Compact Flash chip as shown in Table 3.
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DS583 December 2, 2009
Product Specification