DS583 Datasheet, PDF (7/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Table 4: XPS System ACE Interface Controller I/O Signals (Cont’d)
Port
Signal Name
Interface
I/O
Initial
State
Description
P25 PLB_wrPendPri[0 : 1]
PLB
I
-
PLB pending read
request priority
P26 PLB_reqPri[0 : 1]
PLB
I
-
PLB current request
priority
PLB Slave Interface Signals
P27 Sl_addrack
PLB
O
0
Slave address
acknowledge
P28 Sl_Ssize[0 : 1]
PLB
O
0 Slave data bus size
P29 Sl_wait
PLB
O
0 Slave wait
P30 Sl_rearbitrate
PLB
O
0 Slave bus rearbitrate
P31 Sl_wrDack
PLB
O
0
Slave write data
acknowledge
P32 Sl_wrComp
PLB
O
0
Slave write transfer
complete
P33 Sl_rdBus[0 : C_SPLB_DWIDTH - 1]
PLB
O
0 Slave read data bus
P34 Sl_rdDack
PLB
O
0
Slave read data
acknowledge
P35 Sl_rdComp
PLB
O
0
Slave read transfer
complete
P36 Sl_Mbusy[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Slave busy
P37 Sl_MWrErr[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Slave write error
P38 Sl_MRdErr[0 : C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Slave read error
Unused PLB Slave Interface Signals
P39 Sl_wrBTerm
PLB
O
0
Slave terminate write
burst transfer
P40 Sl_rdWdAddr[0 : 3]
PLB
O
0
Slave read word
address
P41 Sl_rdBTerm
PLB
O
0
Slave terminate read
burst transfer
P42 Sl_MIRQ[0:C_SPLB_NUM_MASTERS - 1]
PLB
O
0 Master interrupt request
System ACE Signals
P43 SysACE_Clk ⁽¹⁾
System
Ace Core
I
- System ACE Clock
P44 SysACE_MPIRQ
System
Ace Core
I
-
System ACE Active high
Interrupt Input
P45 SysACE_CEN
System
Ace Core
O
1
System ACE Chip
Enable
P46 SysACE_OEN
System
Ace Core
O
1 System ACE Enable
P47 SysACE_WEN
System
Ace Core
O
1
System ACE Write
Enable
P48 SysACE_MPA[6 : 0]
System
Ace Core
O
0 System ACE Address
DS583 December 2, 2009
www.xilinx.com
7
Product Specification