DS583 Datasheet, PDF (2/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Functional Description
The XPS SYSACE is composed of the PLB Interface module and the System ACE Interface Controller.
The connections between the XPS System ACE Interface Controller, the PLB Interface module, and the
Xilinx System ACE Controller device are shown in Figure 1
The XPS SYSACE provides the MPU interface to the Xilinx System ACE Controller Device. The Xilinx
System ACE Controller device has multiple interfaces, including CompactFlash, MPU and JTAG. This
allow for a highly flexible configuration solution. The MPU interface of the Xilinx System ACE
Controller device is composed of a set of registers that provide a means for communicating with
CompactFlash control logic, configuration control logic, and other resources in the Xilinx System ACE
Controller device. Specifically, this interface can be used to read the identity of a CompactFlash device
and read/write sectors. The XPS System ACE Interface Controller provides a means of communicating
with the registers and data buffers that correspond to the CompactFlash device in the Xilinx System
ACE Controller device, via the PLB. Refer to the System ACE Interface Controller Flash chip document
mentioned in the <RD Red>Reference Documents section for detailed information on the operation of
the MPU interface, the MPU interface register definitions, and the MPU interface register address map.
The XPS System ACE Interface Controller allows for the registers and data buffers of the Xilinx System
ACE Controller device, to be accessed in a 8-bit and 16-bit data bus access mode. The two modes are
differentiated by the means of the parameter C_MEM_WIDTH, as follows:
• 8-bit mode(C_MEM _WIDTH = 8): The registers are accessed in a 8-bit data bus access mode. In
this mode, the registers of the Xilinx System ACE Controller device should be accessed via byte
accesses only.
• 16-bit mode(C_MEM _WIDTH = 16): The registers are accessed in a 16-bit data bus access mode.
In this mode, the registers of the Xilinx System ACE Controller device should be accessed via
halfword accesses only.
For example, a typical register like the Bus Mode register, is accessed by addresses "00h" and "01h" in
the 8-bit access mode. It would be accessed by address "00h" in the 16-bit access mode.
The software drivers use the C_MEM_WIDTH parameter to configure the Xilinx System ACE Bus
Mode register (setting the Xilinx System ACE MPU data bus access width to the desired mode) and to
access the registers with the proper type of transaction.
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DS583 December 2, 2009
Product Specification