DS583 Datasheet, PDF (13/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Table 10: Performance and Resource Utilization Benchmarks for the Virtex-6 FPGA
(xc6vlx130t-1-ff1156)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR
Slices
Slice Flip-
Flops
LUTs
F_max
(in MHz)
8
30000000
3FFFFFFF
78
268
188
257
16
30000000
3FFFFFFF
75
343
233
267
Table 11: Performance and Resource Utilization Benchmarks for the Spartan-6 FPGA
(xc6slx45t-2-fgg484)
Parameter Values
Device Resources
Performance
C_MEM_WIDTH
C_BASEADDR
C_HIGHADDR
Slices
Slice Flip-
Flops
LUTs
F_max
(in MHz)
8
30000000
3FFFFFFF
74
268
168
153
16
30000000
3FFFFFFF
83
344
216
151
System Performance
To measure the system performance (F_MAX) of this core, this core was added to a Virtex-4 system, a
Virtex-5 system, and a Spartan-3ADSP system as the Device Under Test (DUT) as shown in Figure 8,
Figure 9, and Figure 10.
Because the XPS SYSACE Controller core will be used with other design modules in the FPGA, the
utilization and timing numbers reported in this section are estimates only. When this core is combined
with other designs in the system, the utilization of FPGA resources and timing of the core design will
vary from the results reported here.
X-Ref Target - Figure 8
PLBV46
PLBV46
MPMC5
XPS CDMA XPS CDMA
Device Under
Test (DUT)
IPLB1 DPLB1
DPLB0
PowerPC 405
Processor ^IPLB0
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
DS583_08_101509
Figure 8: Virtex-4 FX FPGA System with the XPS SYSACE Device as the DUT
DS583 December 2, 2009
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Product Specification