DS583 Datasheet, PDF (14/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
X-Ref Target - Figure 9
PLBV46
PLBV46
MMPiirccorrcooeBB_sll_saaozzeer ^™
XCL
XCL
MPMC5
XPS CDMA
XPS CDMA
Device Under
Test (DUT
PowerPC^® 440
Processor
PLBV46
X-Ref Target - Figure 10
MC
PPC440
MC DDR2
MDM
XPS INTC
XPS BRAM
XPS UART
Lite
MDM
DS583_09_101509
Figure 9: Virtex-5 FXT FPGA System with the XPS SYSACE Device as the DUT
MPMC3 XPS CDMA XPS CDMA DUT
MicroBlaze
PLBV46
XPS BRAM XPS INTC
XPS GPIO
XPS UART
Lite
MDM
DS583_10_020509
Figure 10: Spartan-3ADSP FPGA System with the XPS SYSACE Device as the DUT
The target FPGA was then filled with logic to drive the LUT and BRAM utilization to approximately
70% and the I/O utilization to approximately 80%. Using the default tool options and the slowest speed
grade for the target FPGA, the resulting target F_MAX numbers are shown in Table 12.
Table 12: XPS SYSACE Controller Core System Performance
Target FPGA
S3D3400 -4
Target F_MAX (MHz)
100
V4FX60 -10
125
V5FXT70 -1
150
The target F_MAX is influenced by the exact system and is provided for guidance. It is not a guaranteed
value across all systems.
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DS583 December 2, 2009
Product Specification