DS583 Datasheet, PDF (10/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Table 6: XPS System ACE Interface Controller Parameter-Port Dependencies (Cont’d)
Generic
or Port
Parameter
Affects
Depends Relationship Description
P33 Sl_rdBus
-
G5
Width varies with the width of the
PLB Data Bus
P36 Sl_MBusy
-
G8
Width varies with the number of
masters
P37 Sl_MWrErr
-
G8
Width varies with the number of
masters
P38 Sl_MRdErr
-
G8
Width varies with the number of
masters
P49 SysACE_MPD_I
-
G11
Width varies with the width of the
System ACE Data Bus
P50 SysACE_MPD_O
-
G11
Width varies with the width of the
System ACE Data Bus
P51 SysACE_MPD_T
-
G11
Width varies with the width of the
System ACE Data Bus
XPS System ACE Timing Diagrams
This section contains timing diagrams showing the register read and write accesses to the Xilinx System
ACE Interface controller. Note that the System ACE clock is not driven from this core, it is an input to
this core. Also note the byte swapping that occurs during the register accesses. The Figure 4 and
Figure 5 show the 8-bit register write and read cycles.
X-Ref Target - Figure 4
CYCLES
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
SPLB_Clk
PLB_ABus[31:0]
PLB_PAValid
C000007E
PLB_BE[3:0]
PLB_RNW
PLB_wrDBus[31:0]
Sl_wrDAck
2
XXXX73XX
SysACE_Clk
SysACE_CEn
SysACE_OEn
SysACE_WEn
SysACE_MPD[7:0]
SysACE_MPA[6:0]
73
7E
Figure 4: XPS System ACE 8-bit Register Write
DS583_04_101509
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DS583 December 2, 2009
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