DS583 Datasheet, PDF (5/15 Pages) Xilinx, Inc – System ACE Microprocessor Interface

XPS SYSACE (System ACE) Interface Controller (v1.01a)
Table 3: PLB Big Endian to System ACE Little Endian Conversion (done in software driver)
Byte
PLB Data Bus
System ACE Data Bus
MSB
PLB_DBus[0 : 7]
SysACE_MPD[15 : 8]
LSB
PLB_DBus[8 : 15]
SysACE_MPD[7 : 0]
Clocking - SYNC_2_CLKS Module
The controller state machine runs on the SysACE_Clk. The IPIC signals indicating the start of a
transaction are synchronized to the System ACE clock and used to start the state machine. All address,
data and control signals that are output to the System ACE Compact Flash chip are synchronized to the
SysACE_Clk and registered in the FPGA IO registers using SysACE_Clk to ensure a clean interface
between this chip and the FPGA. Data from the System ACE Compact Flash chip is also registered in
FPGA IO registers using SysACE_Clk. It is then synchronized to the SPLB_Clk for transmission on the
bus. The frequency of the SysACE_Clk must be less than the frequency of the SPLB_Clk.
Note that the address and data (if a write transaction) from the PLB will stay stable during the entire
bus transaction and therefore would not have to be synchronized and output using the SysACE_Clk.
This was done to provide a robust design, however, if the overall FPGA design is limited on resources,
these synchronization registers could possibly be removed. The user is cautioned to analyze timing
before removing these registers.
Also note that this core does not instantiate a global clock buffer for SysACE_Clk. This is left for the
user to instantiate based on the resource requirements of their system.
System ACE Control state machine - MEM_STATE_MACHINE Module
The state machine in the System ACE Interface controller performs the specified transaction to the
MPU interface of System ACE Compact Flash chip and is shown in Figure 3. This state machine is
clocked by SysACE_Clk and therefore outputs all System ACE control signals synchronous to this
clock. The input control signals from the PLB Interface Module have been synchronized to the
SysACE_Clk in the sync_2_clocks module.
X-Ref Target - Figure 3
IDLE
idle_rdce_re | sync_wrce_re
ASSERT_CEN
sync_rdce
sync_wrce
IDLE
ASSERT_OEN
ASSERT_WEN
ASSERT_DONE
NEGATE_CEN
DS583_03_101509
Figure 3: System ACE Interface Control State Machine
DS583 December 2, 2009
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