TH58100FT Datasheet, PDF (5/43 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58100FT
Note: (1) CE High to Ready time depends on the pull-up resistor tied to the RY/BY pin.
(Refer to Application Note (9) toward the end of this document.)
(2) Sequential Read is terminated when tCEH is greater than or equal to 100 ns. If the RE to CE delay
is less than 30 ns, RY/BY signal stays Ready.
t_CEH ³ 100 ns
*
*: V_IH or V_IL
CE
RE
525
526
527 A
A : 0 to 30 ns ® Busy signal is not output.
RY/BY
Busy
t_CRY
PROGRAMMING AND ERASING CHARACTERISTICS (Ta = 0° to 70°C, V_CC = 2.7 V to 3.6 V)
SYMBOL
PARAMETER
MIN
t_PROG
Programming Time
¾
t_DBSY
Dummy Busy Time for Multi Block
Programming
¾
t_MBPBSY
Multi Block Program Busy Time
¾
N
Number of Programming Cycles on Same
¾
Page
t_BERASE
Block Erasing Time
¾
(1): Refer to Application Note (12) toward the end of this document.
TYP.
200
2
200
¾
2
MAX
1000
10
1000
3
10
UNIT
ms
ms
ms
ms
NOTES
(1)
2001-03-05 5/43