TH58100FT Datasheet, PDF (21/43 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58100FT
Schematic Cell Layout and Address Assignment
The Program operation works on page units while the Erase operation works on block units.
512
16
262144 pages
8192 blocks
I/O1
I/O8
32 pages
A page consists of 528 bytes in which 512 bytes are used for
main memory storage and 16 bytes are for redundancy or for
other uses.
1 page = 528 bytes
1 block = 528 bytes ´ 32 pages = (16K + 512) bytes
Capacity = 528 bytes ´ 32 pages ´ 8192 blocks
1 block
An address is read in via the I/O port over four consecutive
clock cycles, as shown in Table 1.
8I/O
528
Figure 2. Schematic Cell Layout
Table 1. Addressing
I/O8 I/O7 I/O6 I/O5 I/O4 I/O3 I/O2 I/O1
First cycle
A7 A6 A5 A4 A3 A2 A1 A0
Second cycle
A16 A15 A14 A13 A12 A11 A10 A9
Third cycle
A24 A23 A22 A21 A20 A19 A18 A17
Fourth cycle
*L *L *L *L *L *L A26 A25
* : A8 is automatically set to Low or High by a 00H command or a 01H command.
* : l/O3 to l/O8 must be set to Low in the fourth cycle.
A0 to A7 : Column address
A9 to A26 : Page address
A14 to A26 : Block address
A9 to A13 : NAND address in block
Operation Mode: Logic and Command Tables
The operation modes such as Program, Erase, Read and Reset are controlled by the fourteen different
command operations shown in Table 3. Address input, command input and data input/output are controlled by
the CLE, ALE, CE , WE , RE and WP signals, as shown in Table 2.
Table 2. Logic Table
Command Input
Data Input
Address Input
Serial Data Output
During Programming (Busy)
During Erasing (Busy)
Program, Erase Inhibit
H: V_IH, L: V_IL, *: V_IH or V_IL
CLE
ALE
CE
WE
RE
WP
H
L
L
H
*
L
L
L
H
*
L
H
L
H
*
L
L
L
H
*
*
*
*
*
*
H
*
*
*
*
*
H
*
*
*
*
*
L
2001-03-05 21/43