TH58100FT Datasheet, PDF (23/43 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

TH58100FT
DEVICE OPERATION
Read Mode (1)
Read mode (1) is set when a “00H” command is issued to the Command register. Refer to Figure 3 below for
timing details and the block diagram.
CLE
CE
WE
ALE
RE
RY/BY
N
M
I/O
00H
Busy
Select page
N
Start-address
input
M
527
Cell array
Figure 3. Read mode (1) operation
A data transfer operation from the cell array to the register
starts on the rising edge of WE in the fourth cycle (after the
address information has been latched). The device will be in
Busy state during this transfer period. The CE signal must stay
Low after the fourth address input and during Busy state.
After the transfer period the device returns to Ready state.
Serial data can be output synchronously with the RE clock
from the start pointer designated in the address input cycle.
Read Mode (2)
CLE
CE
WE
ALE
RE
RY/BY
N
M
I/O
01H
Busy
Select page
N
Start-address
input
256 M
527
Cell array
The operation of the device after input of the 01H command is
the same as that of Read mode (1). If the start pointer is to be set
after column address 256, use Read mode (2).
However, for a Sequential Read, output of the next page starts
from column address 0.
Figure 4. Read mode (2) operation
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