TH58100FT Datasheet, PDF(38/43 Page) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TH58100FT Datasheet, PDF (38/43 Pages) Toshiba Semiconductor – TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS

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TH58100FT

(10) Note regarding the WP signal

The Erase and Program operations are automatically reset when WP goes Low. The operations are

enabled and disabled as follows:

Enable Programming

DIN

RY/BY

tWW (100 ns min)

Disable Programming

DIN

RY/BY

tWW (100 ns min)

Enable Erasing

DIN

RY/BY

tWW (100 ns min)

Disable Erasing

DIN

RY/BY

tWW (100 ns min)

2001-03-05 38/43

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