TMS320VC5507_14 Datasheet, PDF (99/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.8.2 Power-Up Reset (On-Chip Oscillator Inactive)
Table 5−12 and Table 5−13 assume testing over recommended operating conditions (see Figure 5−16).
Table 5−12. Power-Up Reset (On-Chip Oscillator Inactive) Timing Requirements
NO.
R2 th(CLKOUTV-RSTL)
Hold time, CLKOUT valid to RESET low
‡ _{P = 1/(input clock frequency) in ns. For example, when input clock is 12 MHz, P = 83.33 ns.}
CVDD = 1.2 V
CVDD = 1.35 V
MIN MAX
3P‡
CVDD = 1.6 V
MIN MAX
3P‡
UNIT
ns
Table 5−13. Power-Up Reset (On-Chip Oscillator Inactive) Switching Characteristics
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V
UNIT
MIN MAX MIN MAX
R3 td(CLKINV-CLKOUTV)
Delay time, CLKIN valid to CLKOUT valid
30
30 ns
X2/CLKIN
CLKOUT
CVDD
DVDD
RESET
R3
R2
Figure 5−16. Power-Up Reset (On-Chip Oscillator Inactive) Timings
April 2004 − Revised January 2008
SPRS244J
99