TMS320VC5507_14 Datasheet, PDF (120/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
CLKOUT†
HINT
† _{CLKOUT reflects the CPU clock.}
E21
Figure 5−31. HINT Timings
HCS
HDS
E13
HR/W
Read
E15
E14
E16
E13
Write
E15
E14
HBE[1:0]
HCNTL0
Valid
Valid
Valid
Valid
HA[13:0]
HD[15:0]
(read)
HD[15:0]
(write)
Valid
E2
E1
E6
Read Data
Valid
E17
E18
Write Data
E7
E8
E10
E9
HRDY
NOTES: A. Any non-multiplexed access with HCNTL0 low will result in HPIC register access. For data read or write, HCNTL0 must stay high
during the EHPI access.
B. The falling edge of HCS must occur concurrent with or before the falling edge of HDS. The rising edge of HCS must occur
concurrent with or after the rising edge of HDS. If HDS1 and/or HDS2 are tied permanently active and HCS is used as a strobe,
the timing requirements shown for HDS apply to HCS. HRDY is always driven to the same value as its internal state.
Figure 5−32. EHPI Nonmultiplexed Read/Write Timings
120 SPRS244J
April 2004 − Revised January 2008