TMS320VC5507_14 Datasheet, PDF (108/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
Table 5−26. McBSP1 and McBSP2 Switching Characteristics^†‡
NO.
PARAMETER
CVDD = 1.2 V
CVDD = 1.35 V
CVDD = 1.6 V _UNIT
MIN MAX
MIN MAX
MC1 tc(CKRX)
MC3 tr(CKRX)
MC4 tf(CKRX)
MC11 tw(CKRXH)
MC12 tw(CKRXL)
Cycle time, CLKR/X
Rise time, CLKR/X
Fall time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
MC13 td(CKRH-FRV) Delay time, CLKR high to internal FSR valid
CLKR/X int
2P
2P
ns
CLKR/X int
2
2 ns
CLKR/X int
2
2 ns
CLKR/X int D − 2§ D + 2§ D − 2§ D + 2§ ns
CLKR/X int C − 2§ C + 2§ C − 2§ C + 2§ ns
CLKR int
CLKR ext
−3
2
−3
3
14
3
2
ns
9
MC14 td(CKXH-FXV) Delay time, CLKX high to internal FSX valid
CLKX int
CLKX ext
−3
2
−3
4
15
4
2
ns
9
Disable time, DX high-impedance from CLKX high ^{CLKX int}
MC15 tdis(CKXH-DXHZ) _{following last data bit}
CLKX ext
−3
3
−5
1
10
19
ns
3
12
Delay time, CLKX high to DX valid.
CLKX int
This applies to all bits except the first bit transmitted. _{CLKX ext}
5
3
15
9
Delay time, CLKX high to DX
valid¶
MC16 td(CKXH-DXV)
DXENA = 0
Only applies to first bit
transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b)
modes
DXENA = 1
CLKX int
CLKX ext
CLKX int
CLKX ext
4
15
2P + 1
2P + 5
2
9 ^ns
2P + 1
2P + 3
Enable time, DX driven from
CLKX high¶
DXENA = 0
MC17 ten(CKXH-DX)
Only applies to first bit
transmitted when in Data Delay 1
or 2 (XDATDLY=01b or 10b)
modes
DXENA = 1
CLKX int
CLKX ext
CLKX int
CLKX ext
−2
9
P−2
P+9
−4
4
ns
P−4
P+4
MC18 td(FXH-DXV)
Delay time, FSX high to DX
valid¶
DXENA = 0
Only applies to first bit
transmitted when in Data Delay 0 ^{DXENA = 1}
(XDATDLY=00b) mode.
FSX int
FSX ext
FSX int
FSX ext
3
13
2P + 1
2P + 12
2
8
ns
2P + 1
2P + 7
MC19 ten(FXH-DX)
Enable time, DX driven from FSX
high¶
DXENA = 0
Only applies to first bit
transmitted when in Data Delay 0 ^{DXENA = 1}
(XDATDLY=00b) mode
FSX int
FSX ext
FSX int
FSX ext
1
8
P−1
P+8
0
4
ns
P−3
P+5
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.}
§ _{T=CLKRX period = (1 + CLKGDV) * P}
C=CLKRX low pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2) * P when CLKGDV is even
D=CLKRX high pulse width = T/2 when CLKGDV is odd or zero and = (CLKGDV/2 + 1) * P when CLKGDV is even
¶ _{See the TMS320C55x DSP Peripherals Overview Reference Guide (literature number SPRU317) for a description of the DX enable (DXENA)}
and data delay features of the McBSP.
108 SPRS244J
April 2004 − Revised January 2008