TMS320VC5507_14 Datasheet, PDF (107/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Electrical Specifications
5.14.2 McBSP1 and McBSP2 Timings
Table 5−25 and Table 5−26 assume testing over recommended operating conditions (see Figure 5−24 and
Figure 5−25).
Table 5−25. McBSP1 and McBSP2 Timing Requirements^†
NO.
MC1 tc(CKRX)
MC2 tw(CKRX)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
CLKR/X ext
CLKR/X ext
CVDD = 1.2 V
CVDD = 1.35 V
MIN MAX
2P‡
P–1‡
CVDD = 1.6 V
MIN
2P‡
P–1‡
MAX
UNIT
ns
ns
MC3 tr(CKRX)
Rise time, CLKR/X
CLKR/X ext
6
6 ns
MC4
MC5
tf(CKRX)
Fall time, CLKR/X
tsu(FRH-CKRL) Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR int
CLKR ext
6
6 ns
11
7
ns
3
3
CLKR int
−3
MC6 th(CKRL-FRH) Hold time, external FSR high after CLKR low
CLKR ext
1
−3
ns
1
CLKR int
11
MC7 tsu(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR ext
3
MC8 th(CKRL-DRV) Hold time, DR valid after CLKR low
CLKR int
−2
CLKR ext
3
CLKX int
14
MC9 tsu(FXH-CKXL) Setup time, external FSX high before CLKX low _{CLKX ext}
4
7
ns
3
−2
ns
3
9
ns
3
CLKX int
−3
MC10 th(CKXL-FXH) Hold time, external FSX high after CLKX low
CLKX ext
1
−3
ns
1
† _{Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of that signal are}
also inverted.
‡ _{P = 1/CPU clock frequency. For example, when running parts at 200 MHz, use P = 5 ns.}
April 2004 − Revised January 2008
SPRS244J 107