TMS320VC5507_14 Datasheet, PDF (38/137 Pages) Texas Instruments – Fixed-Point Digital Signal Processor

Functional Overview
3.4 I²C Interface
The TMS320VC5507 includes an I²C serial port. The I²C port supports:
• Compatible with Philips I²C Specification Revision 2.1 (January 2000)
• Operates at 100 Kbps or 400 Kbps
• 7-bit addressing mode
• Master (transmit/receive) and slave (transmit/receive) modes of operation
• Events: DMA, interrupt, or polling
The I²C module clock must be in the range from 7 MHz to 12 MHz. This is necessary for proper operation of
the I²C module. With the I²C module clock in this range, the noise filters on the SDA and SCL pins suppress
noise that has a duration of 50 ns or shorter. The I²C module clock is derived from the DSP clock divided by
a programmable prescaler.
NOTE: I/O buffers are not fail-safe. The SDA and SCL pins could potentially draw current if the
device is powered down and SDA and SCL are driven by other devices connected to the I²C bus.
3.5 Configurable External Buses
The 5507 offers combinations of configurations for its external parallel port. This allows the system designer
to choose the appropriate media interface for its application without the need of a large-pin-count package.
The External Bus Selection Register controls the routing of the parallel port signals.
38 SPRS244J
April 2004 − Revised January 2008